KR20090042717A - 실리콘 인터포저 및 이를 결합한 반도체 장치 패키지와 반도체 장치 - Google Patents

실리콘 인터포저 및 이를 결합한 반도체 장치 패키지와 반도체 장치 Download PDF

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Publication number
KR20090042717A
KR20090042717A KR1020080101848A KR20080101848A KR20090042717A KR 20090042717 A KR20090042717 A KR 20090042717A KR 1020080101848 A KR1020080101848 A KR 1020080101848A KR 20080101848 A KR20080101848 A KR 20080101848A KR 20090042717 A KR20090042717 A KR 20090042717A
Authority
KR
South Korea
Prior art keywords
hole electrode
silicon interposer
semiconductor device
semiconductor element
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020080101848A
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English (en)
Korean (ko)
Inventor
마사히로 스노하라
Original Assignee
신꼬오덴기 고교 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 신꼬오덴기 고교 가부시키가이샤 filed Critical 신꼬오덴기 고교 가부시키가이샤
Publication of KR20090042717A publication Critical patent/KR20090042717A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
KR1020080101848A 2007-10-26 2008-10-17 실리콘 인터포저 및 이를 결합한 반도체 장치 패키지와 반도체 장치 Withdrawn KR20090042717A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2007-278440 2007-10-26
JP2007278440A JP5248084B2 (ja) 2007-10-26 2007-10-26 シリコンインターポーザとこれを用いた半導体装置用パッケージおよび半導体装置

Publications (1)

Publication Number Publication Date
KR20090042717A true KR20090042717A (ko) 2009-04-30

Family

ID=40474923

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080101848A Withdrawn KR20090042717A (ko) 2007-10-26 2008-10-17 실리콘 인터포저 및 이를 결합한 반도체 장치 패키지와 반도체 장치

Country Status (4)

Country Link
US (1) US20090121344A1 (https=)
EP (1) EP2058858B1 (https=)
JP (1) JP5248084B2 (https=)
KR (1) KR20090042717A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104347548A (zh) * 2013-08-02 2015-02-11 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101167882B1 (ko) 2010-07-20 2012-07-23 (주) 이피웍스 인터포저의 제조 방법
JP5577988B2 (ja) * 2010-09-24 2014-08-27 カシオ計算機株式会社 インターポーザーの製造方法及び半導体装置の製造方法
US20120080318A1 (en) * 2010-10-04 2012-04-05 Gillen James R Forming Through-Substrate Vias by Electrofilling
US9691636B2 (en) 2012-02-02 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Interposer frame and method of manufacturing the same
JP2014011169A (ja) 2012-06-27 2014-01-20 Ps4 Luxco S A R L シリコンインターポーザ及びこれを備える半導体装置
US9070644B2 (en) * 2013-03-15 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors
JP6041731B2 (ja) * 2013-03-27 2016-12-14 新光電気工業株式会社 インターポーザ、及び電子部品パッケージ
JP6191728B2 (ja) 2015-08-10 2017-09-06 大日本印刷株式会社 イメージセンサモジュール
JP6540912B2 (ja) * 2016-12-07 2019-07-10 株式会社村田製作所 電子部品及びその製造方法
KR102713394B1 (ko) 2019-04-15 2024-10-04 삼성전자주식회사 반도체 패키지
US11990418B2 (en) * 2021-08-27 2024-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package structure with buffer structure and method for forming the same

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001035850A (ja) * 1999-07-19 2001-02-09 Ebara Corp 半導体装置及びその製造方法
JP4074862B2 (ja) * 2004-03-24 2008-04-16 ローム株式会社 半導体装置の製造方法、半導体装置、および半導体チップ
JP4426482B2 (ja) * 2005-02-28 2010-03-03 Ｏｋｉセミコンダクタ株式会社 パッケージ基台およびその製造方法、並びにそのパッケージ基台を備えた半導体パッケージ
JP2006313790A (ja) * 2005-05-06 2006-11-16 Matsushita Electric Works Ltd 基板のスルーホール構造
JP4509869B2 (ja) * 2005-06-08 2010-07-21 新光電気工業株式会社 回路基板の製造方法
US7884483B2 (en) * 2005-06-14 2011-02-08 Cufer Asset Ltd. L.L.C. Chip connector
JP4698296B2 (ja) 2005-06-17 2011-06-08 新光電気工業株式会社 貫通電極を有する半導体装置の製造方法
US7402515B2 (en) * 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
JPWO2007032213A1 (ja) * 2005-09-14 2009-03-19 日本電気株式会社 プリント配線基板および半導体パッケージ
US20090266589A1 (en) * 2005-10-14 2009-10-29 Ube Industries, Ltd. Process for producing metal wiring board
JP2007184426A (ja) * 2006-01-06 2007-07-19 Shinko Electric Ind Co Ltd 半導体装置の製造方法
JP2008004927A (ja) * 2006-05-23 2008-01-10 Olympus Corp 積層実装構造体
JP4996285B2 (ja) * 2007-03-01 2012-08-08 津田駒工業株式会社 クランプスリーブ
US20090084425A1 (en) * 2007-09-28 2009-04-02 Erel Milshtein Scribing Methods for Photovoltaic Modules Including a Mechanical Scribe

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104347548A (zh) * 2013-08-02 2015-02-11 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法

Also Published As

Publication number Publication date
JP2009110983A (ja) 2009-05-21
EP2058858A3 (en) 2011-09-14
EP2058858A2 (en) 2009-05-13
JP5248084B2 (ja) 2013-07-31
EP2058858B1 (en) 2018-12-05
US20090121344A1 (en) 2009-05-14

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St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PC1203 Withdrawal of no request for examination

St.27 status event code: N-1-6-B10-B12-nap-PC1203

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St.27 status event code: A-2-2-P10-P22-nap-X000