KR20090009737A - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

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Publication number
KR20090009737A
KR20090009737A KR1020080069978A KR20080069978A KR20090009737A KR 20090009737 A KR20090009737 A KR 20090009737A KR 1020080069978 A KR1020080069978 A KR 1020080069978A KR 20080069978 A KR20080069978 A KR 20080069978A KR 20090009737 A KR20090009737 A KR 20090009737A
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South Korea
Prior art keywords
semiconductor device
electrode terminal
metal wire
semiconductor
metal
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Korean (ko)
Inventor
시게루 미즈노
다카시 구리하라
아키노리 시라이시
게이 무라야마
미츠토시 히가시
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신꼬오덴기 고교 가부시키가이샤
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Publication of KR20090009737A publication Critical patent/KR20090009737A/ko
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    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
KR1020080069978A 2007-07-20 2008-07-18 반도체장치 및 그 제조방법 Withdrawn KR20090009737A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007190030A JP5110995B2 (ja) 2007-07-20 2007-07-20 積層型半導体装置及びその製造方法
JPJP-P-2007-00190030 2007-07-20

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Publication Number Publication Date
KR20090009737A true KR20090009737A (ko) 2009-01-23

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US (1) US20090020887A1 (enExample)
JP (1) JP5110995B2 (enExample)
KR (1) KR20090009737A (enExample)
TW (1) TW200905766A (enExample)

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WO2009035849A2 (en) 2007-09-10 2009-03-19 Vertical Circuits, Inc. Semiconductor die mount by conformal die coating
US8178978B2 (en) 2008-03-12 2012-05-15 Vertical Circuits, Inc. Support mounted electrically interconnected die assembly
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
US7863159B2 (en) 2008-06-19 2011-01-04 Vertical Circuits, Inc. Semiconductor die separation method
WO2010068699A2 (en) * 2008-12-09 2010-06-17 Vertical Circuits, Inc. Semiconductor die interconnect formed by aerosol application of electrically conductive material
JP5112275B2 (ja) * 2008-12-16 2013-01-09 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
JP5136449B2 (ja) * 2009-02-06 2013-02-06 富士通株式会社 半導体装置の製造方法
JP5215244B2 (ja) * 2009-06-18 2013-06-19 新光電気工業株式会社 半導体装置
US9147583B2 (en) 2009-10-27 2015-09-29 Invensas Corporation Selective die electrical insulation by additive process
TWI544604B (zh) 2009-11-04 2016-08-01 英維瑟斯公司 具有降低應力電互連的堆疊晶粒總成
KR102099878B1 (ko) * 2013-07-11 2020-04-10 삼성전자 주식회사 반도체 패키지
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
CN111081687B (zh) * 2019-12-16 2022-02-01 东莞记忆存储科技有限公司 一种堆叠式芯片封装结构及其封装方法
US12456707B2 (en) * 2022-10-06 2025-10-28 Texas Instruments Incorporated Stacked clip design for GaN half bridge IPM

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