KR20070059979A - 반도체 장치 및 데이터 기억장치 - Google Patents

반도체 장치 및 데이터 기억장치 Download PDF

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Publication number
KR20070059979A
KR20070059979A KR1020060121701A KR20060121701A KR20070059979A KR 20070059979 A KR20070059979 A KR 20070059979A KR 1020060121701 A KR1020060121701 A KR 1020060121701A KR 20060121701 A KR20060121701 A KR 20060121701A KR 20070059979 A KR20070059979 A KR 20070059979A
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KR
South Korea
Prior art keywords
data
register
scan
scan register
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020060121701A
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English (en)
Korean (ko)
Inventor
가츠야 나카시마
가즈히로 스즈키
사토시 야마카와
도시유키 니시하라
유키히사 츠네다
Original Assignee
소니 가부시끼 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 소니 가부시끼 가이샤 filed Critical 소니 가부시끼 가이샤
Publication of KR20070059979A publication Critical patent/KR20070059979A/ko
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1036—Read-write modes for single port memories, i.e. having either a random port or a serial port using data shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
KR1020060121701A 2005-12-07 2006-12-04 반도체 장치 및 데이터 기억장치 Withdrawn KR20070059979A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2005354063 2005-12-07
JPJP-P-2005-00354063 2005-12-07
JPJP-P-2006-00138120 2006-05-17
JP2006138120A JP4997824B2 (ja) 2005-12-07 2006-05-17 半導体装置およびデータ記憶装置

Publications (1)

Publication Number Publication Date
KR20070059979A true KR20070059979A (ko) 2007-06-12

Family

ID=38120184

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060121701A Withdrawn KR20070059979A (ko) 2005-12-07 2006-12-04 반도체 장치 및 데이터 기억장치

Country Status (3)

Country Link
US (1) US7565588B2 (https=)
JP (1) JP4997824B2 (https=)
KR (1) KR20070059979A (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7393739B2 (en) * 2006-08-30 2008-07-01 International Business Machines Corporation Demultiplexers using transistors for accessing memory cell arrays
WO2009079014A1 (en) * 2007-12-18 2009-06-25 President And Fellows Of Harvard College Nand implementation for high bandwidth applications
US8243532B2 (en) * 2010-02-09 2012-08-14 Infineon Technologies Ag NVM overlapping write method
US8438433B2 (en) * 2010-09-21 2013-05-07 Qualcomm Incorporated Registers with full scan capability
JP2014049173A (ja) * 2012-09-04 2014-03-17 Toshiba Corp 半導体記憶装置
KR102324537B1 (ko) * 2015-06-12 2021-11-09 삼성전자주식회사 출력 피크 전류를 분산할 수 있는 이미지 센서와 이를 포함하는 이미지 처리 시스템

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62248312A (ja) * 1986-04-21 1987-10-29 Nec Corp 直列並列変換回路
JP2500740B2 (ja) * 1993-04-06 1996-05-29 日本電気株式会社 デュアルポ―トメモリ
JP4204685B2 (ja) * 1999-01-19 2009-01-07 株式会社ルネサステクノロジ 同期型半導体記憶装置
JP4078810B2 (ja) * 2001-03-28 2008-04-23 コニカミノルタビジネステクノロジーズ株式会社 画像処理装置および画像処理システム
KR100418522B1 (ko) * 2001-06-11 2004-02-14 삼성전자주식회사 이동가능한 스페어 메모리 어레이 어드레스를 갖는 불휘발성 반도체 메모리 장치 및 그에 따른 리드방법
JP3625466B2 (ja) * 2003-06-30 2005-03-02 株式会社東芝 半導体装置
US7461242B2 (en) * 2005-11-03 2008-12-02 Ati Technologies Ulc Method and apparatus for providing context switching of logic in an integrated circuit using test scan circuitry

Also Published As

Publication number Publication date
JP2007184068A (ja) 2007-07-19
US20070130488A1 (en) 2007-06-07
JP4997824B2 (ja) 2012-08-08
US7565588B2 (en) 2009-07-21

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20061204

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid