KR20070011408A - 실리콘게르마늄을 사용한 반도체 구조 제조 방법 - Google Patents
실리콘게르마늄을 사용한 반도체 구조 제조 방법 Download PDFInfo
- Publication number
- KR20070011408A KR20070011408A KR1020067022481A KR20067022481A KR20070011408A KR 20070011408 A KR20070011408 A KR 20070011408A KR 1020067022481 A KR1020067022481 A KR 1020067022481A KR 20067022481 A KR20067022481 A KR 20067022481A KR 20070011408 A KR20070011408 A KR 20070011408A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- silicon
- germanium
- semiconductor substrate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6302—Non-deposition formation processes
- H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
- H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
- H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0188—Manufacturing their isolation regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/933—Germanium or silicon or Ge-Si on III-V
Landscapes
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/836,172 | 2004-04-30 | ||
| US10/836,172 US7163903B2 (en) | 2004-04-30 | 2004-04-30 | Method for making a semiconductor structure using silicon germanium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20070011408A true KR20070011408A (ko) | 2007-01-24 |
Family
ID=35187681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020067022481A Withdrawn KR20070011408A (ko) | 2004-04-30 | 2005-04-05 | 실리콘게르마늄을 사용한 반도체 구조 제조 방법 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US7163903B2 (https=) |
| EP (1) | EP1751791A4 (https=) |
| JP (1) | JP2007535814A (https=) |
| KR (1) | KR20070011408A (https=) |
| CN (1) | CN100533679C (https=) |
| TW (1) | TW200605159A (https=) |
| WO (1) | WO2005112094A2 (https=) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008094745A1 (en) * | 2007-01-31 | 2008-08-07 | Freescale Semiconductor Inc. | Electronic device including insulating layers having different strains and a process for forming the electronic device |
| US7714318B2 (en) | 2005-11-08 | 2010-05-11 | Freescale Semiconductor, Inc | Electronic device including a transistor structure having an active region adjacent to a stressor layer |
| US8569858B2 (en) | 2006-12-20 | 2013-10-29 | Freescale Semiconductor, Inc. | Semiconductor device including an active region and two layers having different stress characteristics |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7163903B2 (en) * | 2004-04-30 | 2007-01-16 | Freescale Semiconductor, Inc. | Method for making a semiconductor structure using silicon germanium |
| US7332443B2 (en) * | 2005-03-18 | 2008-02-19 | Infineon Technologies Ag | Method for fabricating a semiconductor device |
| US7439165B2 (en) * | 2005-04-06 | 2008-10-21 | Agency For Sceince, Technology And Reasearch | Method of fabricating tensile strained layers and compressive strain layers for a CMOS device |
| US7265004B2 (en) * | 2005-11-14 | 2007-09-04 | Freescale Semiconductor, Inc. | Electronic devices including a semiconductor layer and a process for forming the same |
| US7560318B2 (en) * | 2006-03-13 | 2009-07-14 | Freescale Semiconductor, Inc. | Process for forming an electronic device including semiconductor layers having different stresses |
| US7882382B2 (en) * | 2006-06-14 | 2011-02-01 | International Business Machines Corporation | System and method for performing computer system maintenance and service |
| US7629220B2 (en) * | 2006-06-30 | 2009-12-08 | Freescale Semiconductor, Inc. | Method for forming a semiconductor device and structure thereof |
| FR2925979A1 (fr) * | 2007-12-27 | 2009-07-03 | Commissariat Energie Atomique | PROCEDE DE FABRICATION D'UN SUBSTRAT SEMICONDUCTEUR SUR ISOLANT COMPRENANT UNE ETAPE D'ENRICHISSEMENT EN Ge LOCALISE |
| US8211786B2 (en) | 2008-02-28 | 2012-07-03 | International Business Machines Corporation | CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication |
| US20090289280A1 (en) * | 2008-05-22 | 2009-11-26 | Da Zhang | Method for Making Transistors and the Device Thereof |
| US8003454B2 (en) * | 2008-05-22 | 2011-08-23 | Freescale Semiconductor, Inc. | CMOS process with optimized PMOS and NMOS transistor devices |
| JP2010182841A (ja) * | 2009-02-05 | 2010-08-19 | Sony Corp | 半導体薄膜の形成方法および半導体薄膜の検査装置 |
| US8828851B2 (en) * | 2012-02-01 | 2014-09-09 | Stmicroeletronics, Inc. | Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering |
| CN103839891A (zh) * | 2012-11-26 | 2014-06-04 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
| FR3088481B1 (fr) * | 2018-11-14 | 2024-06-07 | Commissariat Energie Atomique | Procede de fabrication d’un transistor a effet de champ a jonction alignee avec des espaceurs |
| CN115763222A (zh) * | 2022-11-10 | 2023-03-07 | 华虹半导体(无锡)有限公司 | 解决选择性外基区断层的方法 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5312766A (en) * | 1991-03-06 | 1994-05-17 | National Semiconductor Corporation | Method of providing lower contact resistance in MOS transistors |
| US20010003381A1 (en) * | 1998-05-20 | 2001-06-14 | Marius Orlowski | Method to locate particles of a predetermined species within a solid and resulting structures |
| US6369438B1 (en) | 1998-12-24 | 2002-04-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| JP3884203B2 (ja) | 1998-12-24 | 2007-02-21 | 株式会社東芝 | 半導体装置の製造方法 |
| JP3607194B2 (ja) * | 1999-11-26 | 2005-01-05 | 株式会社東芝 | 半導体装置、半導体装置の製造方法、及び半導体基板 |
| JP2002305293A (ja) * | 2001-04-06 | 2002-10-18 | Canon Inc | 半導体部材の製造方法及び半導体装置の製造方法 |
| JP3647777B2 (ja) | 2001-07-06 | 2005-05-18 | 株式会社東芝 | 電界効果トランジスタの製造方法及び集積回路素子 |
| JP2003031495A (ja) * | 2001-07-12 | 2003-01-31 | Hitachi Ltd | 半導体装置用基板の製造方法および半導体装置の製造方法 |
| US20030096490A1 (en) * | 2001-11-16 | 2003-05-22 | John Borland | Method of forming ultra shallow junctions |
| US6805962B2 (en) * | 2002-01-23 | 2004-10-19 | International Business Machines Corporation | Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications |
| JP3873012B2 (ja) * | 2002-07-29 | 2007-01-24 | 株式会社東芝 | 半導体装置の製造方法 |
| US6759712B2 (en) * | 2002-09-12 | 2004-07-06 | Micron Technology, Inc. | Semiconductor-on-insulator thin film transistor constructions |
| US6998683B2 (en) * | 2002-10-03 | 2006-02-14 | Micron Technology, Inc. | TFT-based common gate CMOS inverters, and computer systems utilizing novel CMOS inverters |
| US6764883B1 (en) * | 2003-01-07 | 2004-07-20 | International Business Machines Corp. | Amorphous and polycrystalline silicon nanolaminate |
| US7042052B2 (en) * | 2003-02-10 | 2006-05-09 | Micron Technology, Inc. | Transistor constructions and electronic devices |
| US7163903B2 (en) * | 2004-04-30 | 2007-01-16 | Freescale Semiconductor, Inc. | Method for making a semiconductor structure using silicon germanium |
| US7312128B2 (en) | 2004-12-01 | 2007-12-25 | Applied Materials, Inc. | Selective epitaxy process with alternating gas supply |
-
2004
- 2004-04-30 US US10/836,172 patent/US7163903B2/en not_active Expired - Fee Related
-
2005
- 2005-04-05 JP JP2007510751A patent/JP2007535814A/ja active Pending
- 2005-04-05 WO PCT/US2005/011552 patent/WO2005112094A2/en not_active Ceased
- 2005-04-05 KR KR1020067022481A patent/KR20070011408A/ko not_active Withdrawn
- 2005-04-05 CN CNB2005800116543A patent/CN100533679C/zh not_active Expired - Fee Related
- 2005-04-05 EP EP05732886A patent/EP1751791A4/en not_active Withdrawn
- 2005-04-22 TW TW094112960A patent/TW200605159A/zh unknown
-
2006
- 2006-12-12 US US11/609,664 patent/US7927956B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7714318B2 (en) | 2005-11-08 | 2010-05-11 | Freescale Semiconductor, Inc | Electronic device including a transistor structure having an active region adjacent to a stressor layer |
| US8569858B2 (en) | 2006-12-20 | 2013-10-29 | Freescale Semiconductor, Inc. | Semiconductor device including an active region and two layers having different stress characteristics |
| US9847389B2 (en) | 2006-12-20 | 2017-12-19 | Nxp Usa, Inc. | Semiconductor device including an active region and two layers having different stress characteristics |
| WO2008094745A1 (en) * | 2007-01-31 | 2008-08-07 | Freescale Semiconductor Inc. | Electronic device including insulating layers having different strains and a process for forming the electronic device |
| US7843011B2 (en) | 2007-01-31 | 2010-11-30 | Freescale Semiconductor, Inc. | Electronic device including insulating layers having different strains |
| US8021957B2 (en) | 2007-01-31 | 2011-09-20 | Freescale Semiconductor, Inc. | Process of forming an electronic device including insulating layers having different strains |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1751791A4 (en) | 2010-02-03 |
| JP2007535814A (ja) | 2007-12-06 |
| WO2005112094A3 (en) | 2007-06-28 |
| US20050245092A1 (en) | 2005-11-03 |
| US7927956B2 (en) | 2011-04-19 |
| TW200605159A (en) | 2006-02-01 |
| CN100533679C (zh) | 2009-08-26 |
| EP1751791A2 (en) | 2007-02-14 |
| CN101147243A (zh) | 2008-03-19 |
| WO2005112094A2 (en) | 2005-11-24 |
| US20070082453A1 (en) | 2007-04-12 |
| WO2005112094A9 (en) | 2009-04-30 |
| US7163903B2 (en) | 2007-01-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| PC1203 | Withdrawal of no request for examination |
St.27 status event code: N-1-6-B10-B12-nap-PC1203 |
|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid | ||
| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-3-3-R10-R18-oth-X000 |
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| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-3-3-R10-R18-oth-X000 |
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| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-3-3-R10-R18-oth-X000 |
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| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-3-3-R10-R18-oth-X000 |
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| PN2301 | Change of applicant |
St.27 status event code: A-3-3-R10-R13-asn-PN2301 St.27 status event code: A-3-3-R10-R11-asn-PN2301 |
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| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |