TW200605159A - Method for making a semiconductor structure using silicon germanium - Google Patents

Method for making a semiconductor structure using silicon germanium

Info

Publication number
TW200605159A
TW200605159A TW094112960A TW94112960A TW200605159A TW 200605159 A TW200605159 A TW 200605159A TW 094112960 A TW094112960 A TW 094112960A TW 94112960 A TW94112960 A TW 94112960A TW 200605159 A TW200605159 A TW 200605159A
Authority
TW
Taiwan
Prior art keywords
silicon
layer
germanium
rich
substrate
Prior art date
Application number
TW094112960A
Other languages
English (en)
Chinese (zh)
Inventor
Marius K Orlowski
Alexander L Barr
Mariam G Sadaka
Ted R White
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200605159A publication Critical patent/TW200605159A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

Landscapes

  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW094112960A 2004-04-30 2005-04-22 Method for making a semiconductor structure using silicon germanium TW200605159A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/836,172 US7163903B2 (en) 2004-04-30 2004-04-30 Method for making a semiconductor structure using silicon germanium

Publications (1)

Publication Number Publication Date
TW200605159A true TW200605159A (en) 2006-02-01

Family

ID=35187681

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094112960A TW200605159A (en) 2004-04-30 2005-04-22 Method for making a semiconductor structure using silicon germanium

Country Status (7)

Country Link
US (2) US7163903B2 (https=)
EP (1) EP1751791A4 (https=)
JP (1) JP2007535814A (https=)
KR (1) KR20070011408A (https=)
CN (1) CN100533679C (https=)
TW (1) TW200605159A (https=)
WO (1) WO2005112094A2 (https=)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7163903B2 (en) * 2004-04-30 2007-01-16 Freescale Semiconductor, Inc. Method for making a semiconductor structure using silicon germanium
US7332443B2 (en) * 2005-03-18 2008-02-19 Infineon Technologies Ag Method for fabricating a semiconductor device
US7439165B2 (en) * 2005-04-06 2008-10-21 Agency For Sceince, Technology And Reasearch Method of fabricating tensile strained layers and compressive strain layers for a CMOS device
US7420202B2 (en) 2005-11-08 2008-09-02 Freescale Semiconductor, Inc. Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device
US7265004B2 (en) * 2005-11-14 2007-09-04 Freescale Semiconductor, Inc. Electronic devices including a semiconductor layer and a process for forming the same
US7560318B2 (en) * 2006-03-13 2009-07-14 Freescale Semiconductor, Inc. Process for forming an electronic device including semiconductor layers having different stresses
US7882382B2 (en) * 2006-06-14 2011-02-01 International Business Machines Corporation System and method for performing computer system maintenance and service
US7629220B2 (en) * 2006-06-30 2009-12-08 Freescale Semiconductor, Inc. Method for forming a semiconductor device and structure thereof
US8569858B2 (en) 2006-12-20 2013-10-29 Freescale Semiconductor, Inc. Semiconductor device including an active region and two layers having different stress characteristics
US7843011B2 (en) * 2007-01-31 2010-11-30 Freescale Semiconductor, Inc. Electronic device including insulating layers having different strains
FR2925979A1 (fr) * 2007-12-27 2009-07-03 Commissariat Energie Atomique PROCEDE DE FABRICATION D'UN SUBSTRAT SEMICONDUCTEUR SUR ISOLANT COMPRENANT UNE ETAPE D'ENRICHISSEMENT EN Ge LOCALISE
US8211786B2 (en) 2008-02-28 2012-07-03 International Business Machines Corporation CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication
US20090289280A1 (en) * 2008-05-22 2009-11-26 Da Zhang Method for Making Transistors and the Device Thereof
US8003454B2 (en) * 2008-05-22 2011-08-23 Freescale Semiconductor, Inc. CMOS process with optimized PMOS and NMOS transistor devices
JP2010182841A (ja) * 2009-02-05 2010-08-19 Sony Corp 半導体薄膜の形成方法および半導体薄膜の検査装置
US8828851B2 (en) * 2012-02-01 2014-09-09 Stmicroeletronics, Inc. Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering
CN103839891A (zh) * 2012-11-26 2014-06-04 中国科学院微电子研究所 一种半导体结构及其制造方法
FR3088481B1 (fr) * 2018-11-14 2024-06-07 Commissariat Energie Atomique Procede de fabrication d’un transistor a effet de champ a jonction alignee avec des espaceurs
CN115763222A (zh) * 2022-11-10 2023-03-07 华虹半导体(无锡)有限公司 解决选择性外基区断层的方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5312766A (en) * 1991-03-06 1994-05-17 National Semiconductor Corporation Method of providing lower contact resistance in MOS transistors
US20010003381A1 (en) * 1998-05-20 2001-06-14 Marius Orlowski Method to locate particles of a predetermined species within a solid and resulting structures
US6369438B1 (en) 1998-12-24 2002-04-09 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP3884203B2 (ja) 1998-12-24 2007-02-21 株式会社東芝 半導体装置の製造方法
JP3607194B2 (ja) * 1999-11-26 2005-01-05 株式会社東芝 半導体装置、半導体装置の製造方法、及び半導体基板
JP2002305293A (ja) * 2001-04-06 2002-10-18 Canon Inc 半導体部材の製造方法及び半導体装置の製造方法
JP3647777B2 (ja) 2001-07-06 2005-05-18 株式会社東芝 電界効果トランジスタの製造方法及び集積回路素子
JP2003031495A (ja) * 2001-07-12 2003-01-31 Hitachi Ltd 半導体装置用基板の製造方法および半導体装置の製造方法
US20030096490A1 (en) * 2001-11-16 2003-05-22 John Borland Method of forming ultra shallow junctions
US6805962B2 (en) * 2002-01-23 2004-10-19 International Business Machines Corporation Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications
JP3873012B2 (ja) * 2002-07-29 2007-01-24 株式会社東芝 半導体装置の製造方法
US6759712B2 (en) * 2002-09-12 2004-07-06 Micron Technology, Inc. Semiconductor-on-insulator thin film transistor constructions
US6998683B2 (en) * 2002-10-03 2006-02-14 Micron Technology, Inc. TFT-based common gate CMOS inverters, and computer systems utilizing novel CMOS inverters
US6764883B1 (en) * 2003-01-07 2004-07-20 International Business Machines Corp. Amorphous and polycrystalline silicon nanolaminate
US7042052B2 (en) * 2003-02-10 2006-05-09 Micron Technology, Inc. Transistor constructions and electronic devices
US7163903B2 (en) * 2004-04-30 2007-01-16 Freescale Semiconductor, Inc. Method for making a semiconductor structure using silicon germanium
US7312128B2 (en) 2004-12-01 2007-12-25 Applied Materials, Inc. Selective epitaxy process with alternating gas supply

Also Published As

Publication number Publication date
EP1751791A4 (en) 2010-02-03
JP2007535814A (ja) 2007-12-06
WO2005112094A3 (en) 2007-06-28
US20050245092A1 (en) 2005-11-03
US7927956B2 (en) 2011-04-19
KR20070011408A (ko) 2007-01-24
CN100533679C (zh) 2009-08-26
EP1751791A2 (en) 2007-02-14
CN101147243A (zh) 2008-03-19
WO2005112094A2 (en) 2005-11-24
US20070082453A1 (en) 2007-04-12
WO2005112094A9 (en) 2009-04-30
US7163903B2 (en) 2007-01-16

Similar Documents

Publication Publication Date Title
TW200605159A (en) Method for making a semiconductor structure using silicon germanium
WO2001084601A3 (en) Implantation process using sub-stoichiometric, oxygen doses at different energies
JP4428520B2 (ja) Ｓｉ１−ｘＧｅｘ層の選択的エッチングを用いるシリコンオンナッシング（ＳＯＮ）ＭＯＳＦＥＴの製造
WO2003044833A3 (en) Method for limiting divot formation in post shallow trench isolation processes
EP1526567A3 (en) Bonded semiconductor device having alignment mark and fabrication method for the same
WO2004093197A3 (en) Method for forming structures in finfet devices
TW200501274A (en) Silicon-on-nothing fabrication process
WO2006127093A3 (en) Methods of fabricating silicon carbide devices having a smooth surface of the channel regions
JP2008010871A (ja) 傾斜側壁表面を備えたソース／ドレイン陥凹部を有するｍｏｓｆｅｔおよびこれを形成するための方法
DE602004012323D1 (de) Katheterspitze
IL178387A0 (en) Method for fabricating strained silicon-on-insulator structures and strained silicon-on-insulator structures formed thereby
TW200504814A (en) Semiconductor device and method for manufacturing semiconductor device
WO2007029178A3 (en) Method of manufacturing a semiconductor device with an isolation region and a device manufactured by the method
TW200636873A (en) Semiconductor fabrication process including recessed source/drain regions in an SOI wafer
WO2002078061A3 (en) RECESSED SILICON OXIDATION FOR DEVICES SUCH AS A CMOS SOI ICs
ATE486365T1 (de) Locos isolation für eine vollständig verarmte soi struktur
TW200701435A (en) Building fully-depleted and partially-depleted transistors on same chip
TW200410371A (en) Structure and method of fabricating a patterned SOI embedded dram having a vertical device cell
TW200707594A (en) Method of forming a semiconductor structure
TW200618290A (en) Semiconductor device and manufacturing method thereof
EP1331662A3 (en) SOI semiconductor device and method for producing the same
WO2003028093A3 (de) Verfahren zur bildung eines soi-substrats, vertikaler transistor und speicherzelle mit vertikalem transistor
WO2005071738A3 (en) Shallow trench isolation process and structure
US9034102B2 (en) Method of fabricating hybrid orientation substrate and structure of the same
WO2006135420A3 (en) Method for simultaneous fabrication of a nanocrystal and non-nanocrystal device