WO2003028093A3 - Verfahren zur bildung eines soi-substrats, vertikaler transistor und speicherzelle mit vertikalem transistor - Google Patents

Verfahren zur bildung eines soi-substrats, vertikaler transistor und speicherzelle mit vertikalem transistor Download PDF

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Publication number
WO2003028093A3
WO2003028093A3 PCT/DE2002/003023 DE0203023W WO03028093A3 WO 2003028093 A3 WO2003028093 A3 WO 2003028093A3 DE 0203023 W DE0203023 W DE 0203023W WO 03028093 A3 WO03028093 A3 WO 03028093A3
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
vertical transistor
memory cell
generation
web regions
Prior art date
Application number
PCT/DE2002/003023
Other languages
English (en)
French (fr)
Other versions
WO2003028093A2 (de
Inventor
Albert Birner
Steffen Breuer
Matthias Goldbach
Joern Luetzen
Dirk Schumann
Original Assignee
Infineon Technologies Ag
Albert Birner
Steffen Breuer
Matthias Goldbach
Joern Luetzen
Dirk Schumann
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Albert Birner, Steffen Breuer, Matthias Goldbach, Joern Luetzen, Dirk Schumann filed Critical Infineon Technologies Ag
Priority to EP02754539A priority Critical patent/EP1425796A2/de
Publication of WO2003028093A2 publication Critical patent/WO2003028093A2/de
Publication of WO2003028093A3 publication Critical patent/WO2003028093A3/de
Priority to US10/792,691 priority patent/US7084043B2/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap

Abstract

Die vorliegende Erfindung betrifft ein Verfahren zur Erzeugung einer Silicon-On-Insulator-Schichtstruktur auf einer Silizium-Oberfläche mit beliebiger Geometrie, mit dem die Silicon-on-Insulator-Struktur auch nur lokal erzeugt werden kann. Das Verfahren umfaßt das Bilden von Mesoporen (10) in dem Silizium-Oberflächenbereich (3), die Oxidation der Mesoporen-Oberfläche unter Bildung von Siliziumoxid und Stegbereichen (22) aus einkristallinem Silizium, die zwischen benachbarten Mesoporen (10) verbleiben, wobei dieser Schritt beendet wird, sobald eine vorgegebene minimale Silizium-Wandstärke der Stegbereiche (22) erreicht ist, das Freilegen der an dem von dem Halbleiter-Substrat (2) abgewandten Ende angeordneten Stegbereiche (22) zwischen benachbarten Mesoporen; und das Durchführen eines selektiven Epitaxieverfahrens, durch das Silizium auf den freigelegten Stegbereichen (22) selektiv gegenüber den Siliziumoxidbereichen (11) aufwächst. Das Verfahren kann verwendet werden, um einen vertikalen Transistor und eine Speicherzelle mit einem derartigen Auswahltransistor herzustellen.
PCT/DE2002/003023 2001-09-07 2002-08-19 Verfahren zur bildung eines soi-substrats, vertikaler transistor und speicherzelle mit vertikalem transistor WO2003028093A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP02754539A EP1425796A2 (de) 2001-09-07 2002-08-19 Verfahren zur bildung eines soi-substrats, vertikaler transistor und speicherzelle mit vertikalem transistor
US10/792,691 US7084043B2 (en) 2001-09-07 2004-03-05 Method for forming an SOI substrate, vertical transistor and memory cell with vertical transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10143936A DE10143936A1 (de) 2001-09-07 2001-09-07 Verfahren zur Bildung eines SOI-Substrats, vertikaler Transistor und Speicherzelle mit vertikalem Transistor
DE10143936.9 2001-09-07

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/792,691 Continuation US7084043B2 (en) 2001-09-07 2004-03-05 Method for forming an SOI substrate, vertical transistor and memory cell with vertical transistor

Publications (2)

Publication Number Publication Date
WO2003028093A2 WO2003028093A2 (de) 2003-04-03
WO2003028093A3 true WO2003028093A3 (de) 2003-08-14

Family

ID=7698081

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/003023 WO2003028093A2 (de) 2001-09-07 2002-08-19 Verfahren zur bildung eines soi-substrats, vertikaler transistor und speicherzelle mit vertikalem transistor

Country Status (5)

Country Link
US (1) US7084043B2 (de)
EP (1) EP1425796A2 (de)
DE (1) DE10143936A1 (de)
TW (1) TW552683B (de)
WO (1) WO2003028093A2 (de)

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Publication number Priority date Publication date Assignee Title
DE10216614B4 (de) * 2002-04-15 2004-06-17 Infineon Technologies Ag Verfahren zur Verstärkung einer dielektrischen Schicht auf einem Halbleitersubstrat an Fehlstellen und Anordnung mit einer verstärkten dielektrischen Schicht
US6967136B2 (en) * 2003-08-01 2005-11-22 International Business Machines Corporation Method and structure for improved trench processing
US20060151845A1 (en) * 2005-01-07 2006-07-13 Shrinivas Govindarajan Method to control interfacial properties for capacitors using a metal flash layer
US7371645B2 (en) * 2005-12-30 2008-05-13 Infineon Technologies Ag Method of manufacturing a field effect transistor device with recessed channel and corner gate device
US7811896B2 (en) * 2007-12-11 2010-10-12 Hvvi Semiconductors, Inc. Semiconductor structure and method of manufacture
US8716116B2 (en) 2010-03-10 2014-05-06 Micron Technology, Inc. Method of forming a DRAM array of devices with vertically integrated recessed access device and digitline
TWI478341B (zh) * 2011-10-31 2015-03-21 茂達電子股份有限公司 功率電晶體元件及其製作方法
US9761580B1 (en) * 2016-11-01 2017-09-12 Micron Technology, Inc. Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors
US10014305B2 (en) * 2016-11-01 2018-07-03 Micron Technology, Inc. Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors
US11562909B2 (en) * 2020-05-22 2023-01-24 Applied Materials, Inc. Directional selective junction clean with field polymer protections
CN112041987B (zh) * 2020-07-24 2023-11-03 长江存储科技有限责任公司 两步l形选择性外延生长

Citations (9)

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US4914628A (en) * 1986-11-19 1990-04-03 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having substrate isolation of a switching transistor and storage capacitor
EP0501119A2 (de) * 1991-01-16 1992-09-02 Canon Kabushiki Kaisha Verfahren zur Herstellung eines Halbleitersubstrats
US5177576A (en) * 1990-05-09 1993-01-05 Hitachi, Ltd. Dynamic random access memory having trench capacitors and vertical transistors
US5256588A (en) * 1992-03-23 1993-10-26 Motorola, Inc. Method for forming a transistor and a capacitor for use in a vertically stacked dynamic random access memory cell
DE19501838A1 (de) * 1995-01-21 1996-07-25 Telefunken Microelectron Verfahren zum Herstellen von SOI-Strukturen
WO1999025026A1 (de) * 1997-11-12 1999-05-20 Epcos Ag Schaltungsstruktur mit mindestens einem kondensator und verfahren zu dessen herstellung
EP0996145A2 (de) * 1998-09-04 2000-04-26 Canon Kabushiki Kaisha Verfahren zur Herstellung von Halbleitersubstraten
EP1009024A1 (de) * 1998-12-10 2000-06-14 STMicroelectronics S.r.l. Herstellungsverfahren für eine SOI-Scheibe
US6262448B1 (en) * 1999-04-30 2001-07-17 Infineon Technologies North America Corp. Memory cell having trench capacitor and vertical, dual-gated transistor

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US201479A (en) * 1878-03-19 Improvement in check-row-planter attachments
US5365097A (en) 1992-10-05 1994-11-15 International Business Machines Corporation Vertical epitaxial SOI transistor, memory cell and fabrication methods
US5641694A (en) * 1994-12-22 1997-06-24 International Business Machines Corporation Method of fabricating vertical epitaxial SOI transistor
US5945686A (en) * 1997-04-28 1999-08-31 Hitachi, Ltd. Tunneling electronic device
DE19931097A1 (de) 1999-07-06 2001-01-11 Gitta Heider Raum- oder Fensterschmuck
DE10055711B4 (de) 2000-11-10 2008-04-30 Qimonda Ag Verfahren zur Herstellung von Grabenkondensatoren
DE10111761A1 (de) 2001-03-12 2002-10-02 Infineon Technologies Ag Anordnung und Verfahren zum rückseitigen Kontaktieren eines Halbleitersubstrats
FR2823377B1 (fr) * 2001-04-06 2004-07-16 St Microelectronics Sa Ligne conductrice haute frequence sur un circuit integre
DE10138981B4 (de) * 2001-08-08 2005-09-08 Infineon Technologies Ag Verfahren zur Bildung von Siliziumoxid durch elektrochemische Oxidation eines Halbleiter-Substrats mit Vertiefungen

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4914628A (en) * 1986-11-19 1990-04-03 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having substrate isolation of a switching transistor and storage capacitor
US5177576A (en) * 1990-05-09 1993-01-05 Hitachi, Ltd. Dynamic random access memory having trench capacitors and vertical transistors
EP0501119A2 (de) * 1991-01-16 1992-09-02 Canon Kabushiki Kaisha Verfahren zur Herstellung eines Halbleitersubstrats
US5256588A (en) * 1992-03-23 1993-10-26 Motorola, Inc. Method for forming a transistor and a capacitor for use in a vertically stacked dynamic random access memory cell
DE19501838A1 (de) * 1995-01-21 1996-07-25 Telefunken Microelectron Verfahren zum Herstellen von SOI-Strukturen
WO1999025026A1 (de) * 1997-11-12 1999-05-20 Epcos Ag Schaltungsstruktur mit mindestens einem kondensator und verfahren zu dessen herstellung
EP0996145A2 (de) * 1998-09-04 2000-04-26 Canon Kabushiki Kaisha Verfahren zur Herstellung von Halbleitersubstraten
EP1009024A1 (de) * 1998-12-10 2000-06-14 STMicroelectronics S.r.l. Herstellungsverfahren für eine SOI-Scheibe
US6262448B1 (en) * 1999-04-30 2001-07-17 Infineon Technologies North America Corp. Memory cell having trench capacitor and vertical, dual-gated transistor

Also Published As

Publication number Publication date
TW552683B (en) 2003-09-11
DE10143936A1 (de) 2003-01-09
WO2003028093A2 (de) 2003-04-03
EP1425796A2 (de) 2004-06-09
US20040197965A1 (en) 2004-10-07
US7084043B2 (en) 2006-08-01

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