KR20060048142A - 수지 시트의 셋트 및 그것을 사용한 세라믹 구조체의제조방법 및 세라믹 구조체 - Google Patents
수지 시트의 셋트 및 그것을 사용한 세라믹 구조체의제조방법 및 세라믹 구조체 Download PDFInfo
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Abstract
Description
수지시트 원료(수지분) 2a/2b | 80%중량감소온도(℃) | 온도차(℃) | 수지시트의 600℃잔사 (%) | |||
Ta | Tb | Tb-Ta | Tc-Tb | |||
실시예1 | IBMA/BMA | 306 | 326 | 20 | 6 | 0.6 |
비교예1 | IBMA/IBMA | 310 | 310 | 0 | 22 | 0.3 |
비교예2 | BMA/IBMA | 326 | 306 | -20 | 26 | 0.5 |
비교예3 | EC/EC | 363 | 363 | 0 | -31 | 4.5 |
비교예4 | - | - | - | - | - | - |
오목부 저면 표면상태 | 오목부 도체부 | 오목부 형상 | 다층 배선기판 층간밀착 불량 | |||
상태 | 단선율(%) | 벽부 | 저부 휨 최대값(㎛) | |||
실시예1 | 이상무 | 이상무 | 0 | 이상무 | 10 | 무 |
비교예1 | 이상무 | 일부침식 | 0 | 이상무 | 13 | 무 |
비교예2 | 일부침식 | 일부침식 | 2 | 이상무 | 18 | 무 |
비교예3 | 침식파괴 | 침식파괴 | 63 | 이상무 | 20 | 무 |
비교예4 | 이상무 | 이상무 | 0 | 변형 | 44 | 유 |
수지시트 원료(수지분) 2a/2b | 80%중량감소온도(℃) | 온도차(℃) | 수지시트의 600℃잔사 (%) | |||
Ta | Tb | Tb-Ta | Tc-Tb | |||
실시예2 | IBMA/BMA | 309 | 328 | 19 | 4 | 0.5 |
비교예5 | IBMA/IBMA | 305 | 305 | 0 | 27 | 0.2 |
비교예6 | BMA/IBMA | 331 | 309 | -22 | 23 | 0.5 |
비교예7 | EC/EC | 358 | 358 | 0 | -26 | 4.3 |
비교예8 | - | - | - | - | - | - |
공동 저면 표면상태 | 공동 저면의 도체부 | 공동 형상 | 다층 배선기판 층간밀착 불량 | ||||
상태 | 단선율(%) | 상부 | 벽부 | 저부 휨 최대값(㎛) | |||
실시예2 | 이상무 | 이상무 | 0 | 이상무 | 이상무 | 11 | 무 |
비교예5 | 이상무 | 일부침식 | 0 | 일부 균열유 | 이상무 | 14 | 무 |
비교예6 | 일부침식 | 일부침식 | 2 | 이상부 | 이상무 | 16 | 무 |
비교예7 | 침식파괴 | 침식파괴 | 58 | 균열유 | 이상무 | 19 | 무 |
비교예8 | 이상무 | 이상무 | 0 | 이상무 | 변형 | 41 | 유 |
Claims (9)
- 세라믹 그린시트를 복수매 적층해 소성함으로써, 표면의 오목부 및 내부의 공동 중 적어도 한쪽을 갖는 세라믹 구조체를 제조하기 위해서 사용되는 수지 시트의 셋트로서,복수의 수지 시트를 포함하고, 각 수지 시트는, 적층되어야 할 세라믹 그린시트의 상기 오목부가 되는 부위 및 상기 공동이 되는 부위에 적재되어, 상기 세라믹 그린시트를 복수매 적층하여 소성할 때에 열분해되어서 제거되고,최상층부의 수지 시트의 80% 중량감소 온도를 Ta℃, 최하층부의 수지 시트의 80% 중량감소 온도를 Tb℃, 상기 수지 시트가 적재되는 상기 세라믹 그린시트에 함유되는 수지 바인더의 20% 중량감소 온도를 Tc℃라고 했을 때에, Ta<Tb≤Tc의 관계를 만족시키는 것을 특징으로 하는 수지 시트의 셋트.
- 제1항에 있어서, 상기 수지 시트는, 600℃에 있어서 99중량%이상 열분해되는 것을 특징으로 하는 수지 시트의 셋트.
- 제1항 또는 제2항에 있어서, 상기 수지 시트는, 수지 비드와, 수지 바인더와, 가소제 및 윤활제 중 하나이상을 함유하는 것을 특징으로 하는 수지 시트의 셋트.
- 세라믹 그린시트를 복수매 적층하여 소성함으로써, 표면의 오목부 및 내부의 공동 중 적어도 한쪽을 갖는 세라믹 구조체를 제조하는 방법에 있어서,적층되어야 할 세라믹 그린시트의 상기 오목부가 되는 부위 및 상기 공동이 되는 부위에 수지 시트를 적재하는 공정;상기 세라믹 그린시트를 복수매 적층하는 공정; 및상기 세라믹 그린시트의 적층체를 소성할 때에 상기 수지 시트를 열분해시켜서 제거하는 공정을 포함하고,최상층부의 수지 시트의 80% 중량감소 온도를 Ta℃, 최하층부의 수지 시트의 80% 중량감소 온도를 Tb℃, 상기 수지 시트가 적재되는 상기 세라믹 그린시트에 함유되는 수지 바인더의 20% 중량감소 온도를 Tc℃라고 했을 때에, Ta<Tb≤Tc의 관계를 만족시키는 것을 특징으로 하는 세라믹 구조체의 제조방법.
- 제4항에 있어서, 상기 세라믹 그린시트의 적층체를 소성할 때에 상기 수지 시트를 열분해시켜서 제거하는 공정은, 상기 Ta℃를 소정시간 유지해서 상기 최상층부의 수지 시트를 열분해시켜서 제거하는 제1 탈바인더 공정과, 상기 Tb℃를 소정시간 유지해서 상기 최하층부의 수지 시트를 열분해시켜서 제거하는 제2 탈바인더 공정을 포함하는 것을 특징으로 하는 세라믹 구조체의 제조방법.
- 세라믹 그린시트를 복수매 적층해 소성함으로써 내부에 공동을 갖는 세라믹 구조체를 제조하는 방법에 있어서,적층되어야 할 세라믹 그린시트의 상기 공동이 되는 부위에 수지 시트를 적재하는 공정; 및상기 세라믹 그린시트를 복수매 적층해서 상기 수지 시트가 충전된 오목부를 갖는 상기 세라믹 그린시트의 적층체를 형성하는 공정을 포함하고,최상층부의 수지 시트의 80% 중량감소 온도를 Ta℃, 최하층부의 수지 시트의 80% 중량감소 온도를 Tb℃, 상기 수지 시트가 적재되는 상기 세라믹 그린시트에 함유되는 수지 바인더의 20% 중량감소 온도를 Tc℃라고 했을 때에, Ta<Tb≤Tc의 관계를 만족시키고,상기 Ta℃를 소정시간 유지해서 상기 최상층부의 수지 시트를 열분해시켜서 제거한 후에 실온까지 강온하는 제1 탈바인더 공정;상기 적층체 상에 상기 수지 시트가 충전된 오목부를 막도록 다른 상기 세라믹 그린시트를 적층하여 내부에 공동을 갖는 적층체를 형성하는 공정; 및상기 Tb℃를 소정시간 유지해서 상기 최하층부의 수지 시트를 열분해시켜서 제거하는 제2 탈바인더 공정을 추가로 포함하는 것을 특징으로 하는 세라믹 구조체의 제조방법.
- 제5항에 있어서, 상기 세라믹 그린시트의 적층체를 소성할 때에 상기 수지 시트를 열분해시켜서 제거하는 공정은, 상기 Tc℃를 넘는 온도를 소정시간 유지하는 제3 탈바인더 공정을 포함하는 것을 특징으로 하는 세라믹 구조체의 제조방법.
- 제6항에 있어서, 상기 Tc℃를 넘는 온도를 소정시간 유지하는 제3 탈바인더 공정을 추가로 포함하는 것을 특징으로 하는 세라믹 구조체의 제조방법.
- 제4항 내지 제8항 중 어느 한 항에 기재된 세라믹 구조체의 제조방법에 의해 제조된, 표면의 오목부 및 내부의 공동 중 적어도 한쪽을 갖는 것을 특징으로 하는 세라믹 구조체.
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KR100717878B1 (ko) * | 2005-12-09 | 2007-05-14 | 한국전자통신연구원 | 파일럿이 삽입된 위성 통신 시스템에서의 차등검출을활용한 프레임 동기 방법 |
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US8974891B2 (en) * | 2007-10-26 | 2015-03-10 | Coi Ceramics, Inc. | Thermal protection systems comprising flexible regions of inter-bonded lamina of ceramic matrix composite material and methods of forming the same |
EP2423993B1 (en) * | 2009-04-24 | 2015-08-12 | NGK Insulators, Ltd. | Manufacturing method for thin board-shaped fired piezoelectric body |
JP5705881B2 (ja) * | 2011-06-29 | 2015-04-22 | 京セラ株式会社 | 反射部材および発光素子搭載用基板、ならびに発光装置 |
US20150273804A1 (en) * | 2014-03-31 | 2015-10-01 | Jiangsu Kentier Wood Co., Ltd. | Wood composite product |
US10748854B2 (en) | 2016-03-16 | 2020-08-18 | Intel Corporation | Stairstep interposers with integrated shielding for electronics packages |
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