KR20050084487A - 플립 칩들 및 플립 칩 어셈블리들을 위한 선택적 언더필 - Google Patents

플립 칩들 및 플립 칩 어셈블리들을 위한 선택적 언더필 Download PDF

Info

Publication number
KR20050084487A
KR20050084487A KR1020057011896A KR20057011896A KR20050084487A KR 20050084487 A KR20050084487 A KR 20050084487A KR 1020057011896 A KR1020057011896 A KR 1020057011896A KR 20057011896 A KR20057011896 A KR 20057011896A KR 20050084487 A KR20050084487 A KR 20050084487A
Authority
KR
South Korea
Prior art keywords
underfill
flip chip
flip
underfill material
electromechanical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020057011896A
Other languages
English (en)
Korean (ko)
Inventor
마크 차슨
잔 댄버
Original Assignee
프리스케일 세미컨덕터, 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 프리스케일 세미컨덕터, 인크. filed Critical 프리스케일 세미컨덕터, 인크.
Publication of KR20050084487A publication Critical patent/KR20050084487A/ko
Ceased legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00333—Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12043—Photo diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/50—Encapsulations or containers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Led Device Packages (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
KR1020057011896A 2002-12-23 2003-12-11 플립 칩들 및 플립 칩 어셈블리들을 위한 선택적 언더필 Ceased KR20050084487A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/328,326 2002-12-23
US10/328,326 US6800946B2 (en) 2002-12-23 2002-12-23 Selective underfill for flip chips and flip-chip assemblies

Publications (1)

Publication Number Publication Date
KR20050084487A true KR20050084487A (ko) 2005-08-26

Family

ID=32594434

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020057011896A Ceased KR20050084487A (ko) 2002-12-23 2003-12-11 플립 칩들 및 플립 칩 어셈블리들을 위한 선택적 언더필

Country Status (5)

Country Link
US (1) US6800946B2 (enExample)
JP (1) JP2006511964A (enExample)
KR (1) KR20050084487A (enExample)
AU (1) AU2003296497A1 (enExample)
WO (1) WO2004061934A1 (enExample)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7821139B2 (en) 2006-11-29 2010-10-26 Samsung Electronics Co., Ltd. Flip-chip assembly and method of manufacturing the same
WO2013101668A1 (en) * 2011-12-27 2013-07-04 Intel Corporation Barrier tape for keep-out zone management
KR20140086828A (ko) * 2012-12-28 2014-07-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 패키지 강화용 장치 및 방법
US9240387B2 (en) 2011-10-12 2016-01-19 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level chip scale package with re-workable underfill
US9287143B2 (en) 2012-01-12 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus for package reinforcement using molding underfill
US9892962B2 (en) 2015-11-30 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package interconnects and methods of manufacture thereof
US10262964B2 (en) 2013-03-11 2019-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same

Families Citing this family (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4417596B2 (ja) * 2001-09-19 2010-02-17 富士通株式会社 電子部品の実装方法
JP2003309271A (ja) * 2002-04-18 2003-10-31 Matsushita Electric Ind Co Ltd 集積回路素子の実装構造および実装方法
US6916684B2 (en) * 2003-03-18 2005-07-12 Delphi Technologies, Inc. Wafer-applied underfill process
US7042106B2 (en) * 2003-06-24 2006-05-09 Intel Corporation Underfill integration for optical packages
US6834133B1 (en) * 2003-08-27 2004-12-21 Intel Corporation Optoelectronic packages and methods to simultaneously couple an optoelectronic chip to a waveguide and substrate
US7359211B2 (en) * 2004-03-02 2008-04-15 Intel Corporation Local control of underfill flow on high density packages, packages and systems made therewith, and methods of making same
KR100716918B1 (ko) * 2004-03-18 2007-05-10 가부시키가이샤 무라타 세이사쿠쇼 탄성표면파 장치
US7244634B2 (en) 2004-03-31 2007-07-17 Intel Corporation Stress-relief layer and stress-compensation collar in contact arrays, and processes of making same
US20050224951A1 (en) * 2004-03-31 2005-10-13 Daewoong Suh Jet-dispensed stress relief layer in contact arrays, and processes of making same
US20050224967A1 (en) * 2004-04-01 2005-10-13 Brandenburg Scott D Microelectronic assembly with underchip optical window, and method for forming same
US7129417B2 (en) * 2004-04-29 2006-10-31 International Business Machines Corporation Method and structures for implementing customizable dielectric printed circuit card traces
US7183622B2 (en) * 2004-06-30 2007-02-27 Intel Corporation Module integrating MEMS and passive components
TWM271321U (en) * 2004-09-10 2005-07-21 Aiptek Int Inc Flip-chip packaging device
TWI239079B (en) * 2004-09-22 2005-09-01 Advanced Semiconductor Eng Process of fabricating flip chip package and method of forming underfill thereof
DE102005015109B4 (de) * 2005-04-01 2007-06-21 Robert Bosch Gmbh Verfahren zum Montieren von Halbleiterchips auf einem Substrat und entsprechende Anordnung
US7038321B1 (en) * 2005-04-29 2006-05-02 Delphi Technologies, Inc. Method of attaching a flip chip device and circuit assembly formed thereby
CN100372086C (zh) * 2005-05-26 2008-02-27 宏齐科技股份有限公司 具有控制芯片的光电芯片双片式基材封装构造的制造方法
US7736945B2 (en) * 2005-06-09 2010-06-15 Philips Lumileds Lighting Company, Llc LED assembly having maximum metal support for laser lift-off of growth substrate
US7754507B2 (en) * 2005-06-09 2010-07-13 Philips Lumileds Lighting Company, Llc Method of removing the growth substrate of a semiconductor light emitting device
US8335084B2 (en) * 2005-08-01 2012-12-18 Georgia Tech Research Corporation Embedded actives and discrete passives in a cavity within build-up layers
WO2007015683A1 (en) * 2005-08-04 2007-02-08 Infineon Technologies Ag An integrated circuit package and a method for forming an integrated circuit package
DE102005037948A1 (de) * 2005-08-11 2007-02-15 Robert Bosch Gmbh Sensoranordnung mit einem Sensorbauelement und einem Träger und Verfahren zur Herstellung einer Sensoranordnung
JP4750525B2 (ja) * 2005-10-14 2011-08-17 キヤノン株式会社 露光方法及びデバイス製造方法
US7408243B2 (en) * 2005-12-14 2008-08-05 Honeywell International Inc. High temperature package flip-chip bonding to ceramic
US20070145595A1 (en) * 2005-12-27 2007-06-28 Hall Stephen H High speed interconnect
JP4788436B2 (ja) * 2006-03-29 2011-10-05 日本電気株式会社 無線リソース割り当て方法及びそれを用いる無線リソース割り当て装置並びに基地局
US8129463B2 (en) * 2006-03-31 2012-03-06 Applied Nanotech Holdings, Inc. Carbon nanotube-reinforced nanocomposites
US20080090951A1 (en) * 2006-03-31 2008-04-17 Nano-Proprietary, Inc. Dispersion by Microfluidic Process
US20110160346A1 (en) * 2006-03-31 2011-06-30 Applied Nanotech Holdings, Inc. Dispersion of carbon nanotubes by microfluidic process
US20070276077A1 (en) * 2006-04-05 2007-11-29 Nano-Proprietary, Inc. Composites
US8283403B2 (en) * 2006-03-31 2012-10-09 Applied Nanotech Holdings, Inc. Carbon nanotube-reinforced nanocomposites
US8445587B2 (en) * 2006-04-05 2013-05-21 Applied Nanotech Holdings, Inc. Method for making reinforced polymer matrix composites
US20070269930A1 (en) * 2006-05-19 2007-11-22 Texas Instruments Incorporated Methodology to control underfill fillet size, flow-out and bleed in flip chips (FC), chip scale packages (CSP) and ball grid arrays (BGA)
CN101529584B (zh) * 2006-10-19 2010-09-08 松下电器产业株式会社 半导体元件的安装结构体及半导体元件的安装方法
CN101605855A (zh) * 2007-02-09 2009-12-16 柯尼卡美能达精密光学株式会社 光学元件、电子模块以及电子模块的制造方法
US9063117B2 (en) * 2007-02-21 2015-06-23 Paul L. Gourley Micro-optical cavity with fluidic transport chip for bioparticle analysis
KR100871710B1 (ko) * 2007-04-25 2008-12-08 삼성전자주식회사 플립 칩 패키지 및 그 패키지 제조방법
US7993940B2 (en) * 2007-12-05 2011-08-09 Luminus Devices, Inc. Component attach methods and related device structures
JP2009188011A (ja) * 2008-02-04 2009-08-20 Nec Electronics Corp フリップチップ半導体装置の製造方法と製造装置
KR101019151B1 (ko) * 2008-06-02 2011-03-04 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US7777186B2 (en) * 2008-08-14 2010-08-17 L-3 Communications Cincinnati Electronics Corporation Pixel interconnect insulators and methods thereof
US8069730B2 (en) 2008-11-14 2011-12-06 Kulite Semiconductor Products, Inc. Pressure transducer structures suitable for curved surfaces
US9299661B2 (en) * 2009-03-24 2016-03-29 General Electric Company Integrated circuit package and method of making same
US20110156261A1 (en) * 2009-03-24 2011-06-30 Christopher James Kapusta Integrated circuit package and method of making same
JP5261255B2 (ja) * 2009-03-27 2013-08-14 ルネサスエレクトロニクス株式会社 半導体装置
US8451620B2 (en) * 2009-11-30 2013-05-28 Micron Technology, Inc. Package including an underfill material in a portion of an area between the package and a substrate or another package
US8574960B2 (en) * 2010-02-03 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material
JP5418367B2 (ja) * 2010-03-30 2014-02-19 富士通株式会社 プリント配線板ユニットおよび電子機器
US9620934B2 (en) * 2010-08-31 2017-04-11 Avago Technologies General Ip (Singapore) Pte. Ltd. Flip-chip assembly comprising an array of vertical cavity surface emitting lasers (VCSELs)
US9188751B2 (en) 2010-08-31 2015-11-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Flip-chip assembly comprising an array of vertical cavity surface emitting lasers (VCSELSs), and an optical transmitter assembly that incorporates the flip-chip assembly
JP5644286B2 (ja) * 2010-09-07 2014-12-24 オムロン株式会社 電子部品の表面実装方法及び電子部品が実装された基板
US9551844B2 (en) 2011-01-11 2017-01-24 Hewlett Packard Enterprise Development Lp Passive optical alignment
US8796075B2 (en) 2011-01-11 2014-08-05 Nordson Corporation Methods for vacuum assisted underfilling
KR20120091839A (ko) * 2011-02-10 2012-08-20 삼성전자주식회사 플립칩 발광소자 패키지 및 그 제조 방법
US8440543B2 (en) * 2011-09-19 2013-05-14 Teledyne Scientific & Imaging, Llc Hybrid circuit structure and partial backfill method for improving thermal cycling reliability of same
KR20140120885A (ko) * 2012-01-31 2014-10-14 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. 옵토-일렉트로닉 엔진을 위한 콤비네이션 언더필-댐 및 전기적-상호접속 구조체
US9202714B2 (en) 2012-04-24 2015-12-01 Micron Technology, Inc. Methods for forming semiconductor device packages
US9511393B2 (en) * 2012-08-17 2016-12-06 The Boeing Company Flexible ultrasound inspection system
CN102891240B (zh) * 2012-09-18 2015-07-08 惠州雷曼光电科技有限公司 倒装结构的发光二极管及其制备方法
EP2943980B1 (en) * 2013-01-09 2020-08-19 NXP USA, Inc. Electronic high frequency device
JP2014146648A (ja) * 2013-01-28 2014-08-14 Fujikura Ltd 光学素子実装基板およびその製造方法
US20140209961A1 (en) * 2013-01-30 2014-07-31 Luxo-Led Co., Limited Alternating current light emitting diode flip-chip
TWI483434B (zh) * 2013-02-18 2015-05-01 Lextar Electronics Corp 發光二極體的轉置基材與使用該轉置基材的發光裝置製造方法
JP6212985B2 (ja) * 2013-06-27 2017-10-18 住友電気工業株式会社 受光装置、及び、ハイブリッド型イメージセンサ
US9627346B2 (en) * 2013-12-11 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Underfill pattern with gap
JP2015119077A (ja) * 2013-12-19 2015-06-25 ソニー株式会社 半導体装置およびその製造方法
US10345571B2 (en) 2014-01-30 2019-07-09 Karl Storz Endovision, Inc. Intelligent light source
US9373559B2 (en) 2014-03-05 2016-06-21 International Business Machines Corporation Low-stress dual underfill packaging
KR102301869B1 (ko) * 2014-10-20 2021-09-15 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 발광 소자 패키지
DE102015218355A1 (de) * 2015-09-24 2017-03-30 Robert Bosch Gmbh Mikroelektronische Bauelementanordnung und Herstellungsverfahren für eine mikroelektronische Bauelementanordnung
US9798088B2 (en) * 2015-11-05 2017-10-24 Globalfoundries Inc. Barrier structures for underfill blockout regions
US9721812B2 (en) * 2015-11-20 2017-08-01 International Business Machines Corporation Optical device with precoated underfill
US9818655B2 (en) 2015-12-08 2017-11-14 International Business Machines Corporation Method and structure for flip-chip package reliability monitoring using capacitive sensors groups
JP2017195327A (ja) * 2016-04-22 2017-10-26 住友電気工業株式会社 半導体受光装置
US9798087B1 (en) 2016-11-01 2017-10-24 Hewlett Packard Enterprise Development Lp Optoelectronic devices and wavelength-division multiplexing optical connectors
JP6933794B2 (ja) * 2016-12-01 2021-09-08 富士通株式会社 光モジュール及び光モジュールの製造方法
US10276479B1 (en) 2017-10-11 2019-04-30 Micron Technology, Inc. Methods of processing semiconductor devices
TWI672820B (zh) * 2018-02-06 2019-09-21 Luxnet Corporation 光接收器及其製備方法
US11199673B2 (en) * 2019-07-31 2021-12-14 Hewlett Packard Enterprise Development Lp Optoelectronic device with integrated underfill exclusion structure
US11152226B2 (en) 2019-10-15 2021-10-19 International Business Machines Corporation Structure with controlled capillary coverage
US11557491B2 (en) 2019-10-31 2023-01-17 Nxp B.V. Selective underfill assembly and method therefor
KR102517379B1 (ko) 2020-02-14 2023-03-31 삼성전자주식회사 반도체 패키지의 제조 방법
CN113658880B (zh) * 2020-05-12 2025-06-17 联华电子股份有限公司 芯片键合应力的测量方法及芯片键合辅助结构
JP7423423B2 (ja) 2020-05-28 2024-01-29 株式会社日立製作所 半導体検出器およびその製造方法
EP4016620A1 (en) 2020-12-16 2022-06-22 Nxp B.V. Package with an integrated circuit die and a waveguide launcher
JP7617751B2 (ja) * 2021-01-25 2025-01-20 古河電気工業株式会社 光学装置、光学装置のサブアセンブリ、および光学装置の製造方法
US11963291B2 (en) 2022-04-21 2024-04-16 Nxp B.V. Efficient wave guide transition between package and PCB using solder wall
US20240079371A1 (en) * 2022-09-02 2024-03-07 Globalfoundries U.S. Inc. Thermal performance for radio frequency (rf) chip packages
WO2024220219A1 (en) * 2023-04-17 2024-10-24 Ciena Corporation Managing adhesive material shaping using structure arrays
US20240345336A1 (en) * 2023-04-17 2024-10-17 Ciena Corporation Managing adhesive material shaping using structure arrays

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08250542A (ja) * 1995-03-07 1996-09-27 Matsushita Electric Ind Co Ltd 電子部品および電子部品の実装構造
US6140144A (en) * 1996-08-08 2000-10-31 Integrated Sensing Systems, Inc. Method for packaging microsensors
US5867368A (en) * 1997-09-09 1999-02-02 Amkor Technology, Inc. Mounting for a semiconductor integrated circuit device
US5969461A (en) * 1998-04-08 1999-10-19 Cts Corporation Surface acoustic wave device package and method
FR2780200B1 (fr) * 1998-06-22 2003-09-05 Commissariat Energie Atomique Dispositif et procede de formation d'un dispositif presentant une cavite a atmosphere controlee
JP3451987B2 (ja) * 1998-07-01 2003-09-29 日本電気株式会社 機能素子及び機能素子搭載用基板並びにそれらの接続方法
JP2000286301A (ja) * 1999-03-31 2000-10-13 Towa Corp 半導体チップ組立方法及び組立装置
US6490166B1 (en) * 1999-06-11 2002-12-03 Intel Corporation Integrated circuit package having a substrate vent hole
US6700209B1 (en) * 1999-12-29 2004-03-02 Intel Corporation Partial underfill for flip-chip electronic packages
JP2001298102A (ja) * 2000-04-13 2001-10-26 Nec Corp 機能素子の実装構造およびその製造方法
US6499215B1 (en) * 2000-06-29 2002-12-31 International Business Machines Corporation Processing of circuit boards with protective, adhesive-less covers on area array bonding sites
JP3764640B2 (ja) * 2000-09-26 2006-04-12 京セラ株式会社 光モジュール及びその製造方法
JP3867565B2 (ja) * 2000-12-12 2007-01-10 日立化成工業株式会社 基板の接続方法および半導体パッケージの製造方法
JP4044790B2 (ja) * 2001-06-15 2008-02-06 株式会社リコー 半導体装置、画像読取ユニット及び画像形成装置

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7821139B2 (en) 2006-11-29 2010-10-26 Samsung Electronics Co., Ltd. Flip-chip assembly and method of manufacturing the same
US9240387B2 (en) 2011-10-12 2016-01-19 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level chip scale package with re-workable underfill
WO2013101668A1 (en) * 2011-12-27 2013-07-04 Intel Corporation Barrier tape for keep-out zone management
US9287143B2 (en) 2012-01-12 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus for package reinforcement using molding underfill
KR20140086828A (ko) * 2012-12-28 2014-07-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 패키지 강화용 장치 및 방법
US10262964B2 (en) 2013-03-11 2019-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US10714442B2 (en) 2013-03-11 2020-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US11043463B2 (en) 2013-03-11 2021-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9892962B2 (en) 2015-11-30 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package interconnects and methods of manufacture thereof

Also Published As

Publication number Publication date
US20040118599A1 (en) 2004-06-24
WO2004061934A1 (en) 2004-07-22
US6800946B2 (en) 2004-10-05
AU2003296497A1 (en) 2004-07-29
JP2006511964A (ja) 2006-04-06

Similar Documents

Publication Publication Date Title
KR20050084487A (ko) 플립 칩들 및 플립 칩 어셈블리들을 위한 선택적 언더필
KR101010159B1 (ko) 얇은 언더필 및 두꺼운 솔더 마스크를 가지는 플립-칩어셈블리
JP6162114B2 (ja) 光電子モジュール、光電子モジュールの製造方法、ならびに光電子モジュールを備える機器およびデバイス
US6754407B2 (en) Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board
KR20140120884A (ko) 광전자에 사용하기 위한 장치
US7199400B2 (en) Semiconductor package
KR102715554B1 (ko) 반도체 패키지 및 반도체 패키지 제조 방법
US20090152741A1 (en) Chip structure and fabrication process thereof and flip chip package structure and fabrication process thereof
US6765801B1 (en) Optical track drain package
JP2003215371A (ja) 光モジュール及び光モジュールの実装方法
JP2008512851A (ja) ウエハー水準でカメラモジュールを製造する方法
US7841781B2 (en) Methods and apparatuses for providing a hermetic sealing system for an optical transceiver module
US20170148955A1 (en) Method of wafer level packaging of a module
US20140037247A1 (en) Apparatus for use in optoelectronics having a sandwiched lens
KR100957338B1 (ko) 광섬유 엔진 제조 방법
US20170146741A1 (en) Optical device with precoated underfill
US6762119B2 (en) Method of preventing solder wetting in an optical device using diffusion of Cr
US6984866B1 (en) Flip chip optical semiconductor on a PCB
US11199673B2 (en) Optoelectronic device with integrated underfill exclusion structure
US20110089438A1 (en) Opto-electrical assemblies and associated apparatus and methods
CN113970816B (zh) 光波导连接组件及包含光波导连接组件的光学模组
JP4782522B2 (ja) 光機能素子パッケージ及びその製造方法
JP2005064303A (ja) 光電気複合基板装置及びその製造方法
US7956435B2 (en) Semiconductor device
CN118426118A (zh) Cpo光模块封装结构及其晶圆级封装方法

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20050623

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20081211

Comment text: Request for Examination of Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20101130

Patent event code: PE09021S01D

E601 Decision to refuse application
PE0601 Decision on rejection of patent

Patent event date: 20110228

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 20101130

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I