Classifications

• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
  • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
  • B81C1/00261—Processes for packaging MEMS devices
  • B81C1/00333—Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
  • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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  • H01L23/00—Details of semiconductor or other solid state devices
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  • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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  • H01L24/10—Bump connectors ; Manufacturing methods related thereto
  • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
  • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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  • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
  • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
  • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
  • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
  • H01L2224/0554—External layer
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  • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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  • H01L2224/27—Manufacturing methods
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  • H01L2224/29001—Core members of the layer connector
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  • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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  • H01L2224/732—Location after the connecting process
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  • H01L2224/732—Location after the connecting process
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  • H01L2224/838—Bonding techniques
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  • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
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  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F77/00—Constructional details of devices covered by this subclass
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  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
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  • H10H20/85—Packages
  • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
  • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Definitions

• This invention relates generally to semiconductor wafer processing and integrated circuit packaging.
• the invention relates to a selective underfill for opto-electronic and electromechanical bumped semiconductor wafers, flip chips and flip-chip assemblies, and a method for manufacturing a semiconductor wafer, flip chip or a flip- chip module with selective underfill.
• Electromechanical devices such as surface acoustic wave (SAW) devices, micro-electro-mechanical system (MEMS) devices, integrated electromechanical devices, and other devices with movable parts may function in a degraded manner or not function at all if covered with an underfill material. These devices must remain free of underfill material when bumped and used in flip-chip assemblies.
• SAW surface acoustic wave
• MEMS micro-electro-mechanical system
• integrated electromechanical devices and other devices with movable parts may function in a degraded manner or not function at all if covered with an underfill material. These devices must remain free of underfill material when bumped and used in flip-chip assemblies.
• underfill materials are typically applied to the entire surface of the IC interface.
• the underfill is applied at the edges of the flip-chip bonded die and capillary action wicks the fluid under the die. During this process, the entire die surface is coated with the underfill.
• the underfill may be applied to the PWB prior to die placement. During solder reflow, the underfill liquifies and wets the entire die surface. In both cases, the underfill covers the entire die surface and interferes with light propagation between the die emitter and the die detector. If the underfill material is opaque and covers the optical elements, no radiation is transmitted.
• Electromechanical devices with mechanically or acoustically moving structures such as piezoelectric devices or surface-micromachined relays can have no underfill material covering the electromechanical element without impairing operation of the device.
• An underfill material may be applied around the periphery of the flip- chip assembly and partially wicked into the interior region, leaving portions of the flip chip free of the underfill material, as described in US patent 6,365,441 , "Partial Underfill for Flip Chip Electronic Packages" issued April 2, 2002.
• a transparent underfill resin with an index of refraction less than the index of a waveguide cladding is used as an underfill material between optical devices on a flip chip and a printed wiring board.
• the packaging technology would allow the flip chip to be bonded effectively to a substrate, with highly reliable electrical interconnections and protective underfill material for secure die bonding, stress relief for the bumps and effective environmental protection, while retaining unrestricted free-space transmission characteristics between associated optical devices. It would be critical for electromechanical flip chips to be attached to a substrate or PWB without impeding movement of the flip chip when bonded to the PWB or package substrate.
• One aspect of the invention provides a method for attaching a flip chip to a printed wiring board.
• An underfill material is applied to a first portion of a bumped flip chip, maintaining an optical portion or an electromechanical portion of the flip chip free of the underfill material.
• the flip chip with the selective underfill is positioned on a printed wiring board, and heated to electrically and mechanically connect the flip chip to the printed wiring board while the optical portion or electromechanical portion of the flip chip remains free of the underfill material.
• a flip-chip assembly including a bumped flip chip with a first portion and a second portion, and an underfill material selectively disposed on the first portion of the flip chip.
• the second portion of the flip chip may contain one or more optical devices or electromechanical devices.
• the second portion of the flip chip remains free from the underfill material when the flip chip is placed on a printed wiring board and heated to electrically connect the flip chip to the printed wiring board.
• the flip-chip assembly may include a printed wiring board, wherein an active surface of the flip chip is positioned and secured to the printed wiring board, with at least one opto-electronic device on the flip chip optically coupled to an associated device on the printed wiring board.
• a bumped semiconductor wafer including at least one opto-electronic device or electromechanical device and at least one solder bump is aligned to a patterned mask.
• the patterned mask includes at least one barrier feature corresponding to at least one opto-electronic or electromechanical device.
• An underfill material is dispensed through the patterned mask onto the bumped semiconductor wafer, keeping the opto-electronic and electromechanical devices free of the underfill material.
• the underfill material is heated to flow the underfill material around the solder bumps, while the opto-electronic or electromechanical device remains free from the underfill material.
• a bumped semiconductor wafer including at least one opto-electronic device or electromechanical device and at least one solder bump is aligned to the patterned underfill film, the patterned underfill film including a backing layer and an underfill material disposed on the backing layer with at least one open feature in the underfill material corresponding to the opto-electronic or electromechanical device.
• the patterned underfill film is laminated to the bumped semiconductor wafer, the backing layer is removed, and the underfill material is heated to flow the material around the at least one solder bump.
• FIG. 1 illustrates an opto-electronic flip-chip assembly with non- selective underfill, as is typical in the prior art
• FIG. 2 illustrates an opto-electronic or electromechanical flip-chip assembly with selective underfill, in accordance with one embodiment of the current invention
• FIG. 3 illustrates a cross-sectional view of a bumped opto-electronic or electromechanical flip chip with selective underfill, in accordance with one embodiment of the current invention
• FIG. 4 illustrates a plan view of a bumped opto-electronic or electromechanical flip chip with selective underfill, in accordance with one embodiment of the current invention
• FIG. 5 illustrates a block diagram of a method for attaching an optoelectronic or electromechanical flip chip to a printed wiring board, in accordance with one embodiment of the current invention
• FIG. 6 illustrates a block diagram of a selective underfill process, in accordance with one embodiment of the current invention
• FIG. 7 illustrates a block diagram of a selective underfill process, in accordance with another embodiment of the current invention.
• the present invention provides an opto-electronic or electromechanical flip-chip assembly with selective underfill.
• One aspect of the invention is a method for attaching an opto-electronic or electromechanical flip-chip to a printed wiring board.
• the flip-chip underfill assembly process selectively disposes an underfill material on a non-optical portion and non- electromechanical portion of the flip chip.
• the underfill material is limited from covering certain regions of the die.
• the underfill material may be placed on the die surface over non-optical and non- electromechanical portions of the die.
• the underfill material is omitted over optical devices and opto-electronic devices such as light emitters and detectors where the underfill material could limit or prohibit the transmission of light between the flip chip and the substrate or printed wiring board.
• the underfill material may also be restricted from other areas of the die or wafer, such as the die streets or on top of the solder bumps, or from selected regions of solder bumps on the flip chip.
• the underfill material has sufficient viscosity during application to the flip chip so that selected regions of the die are left open and free of the underfill material.
• the underfill material may flow outwardly to form a fillet at the die edges, although it does not collapse internally around the optically active areas. Fillets may also be formed at the interior edges of the underfill material.
• the invention can be applied to any opto-electronic assembly that requires the opto-electronic die to be flip-chip assembled using underfill.
• the invention can also be applied to any electromechanical assembly that requires the electromechanical die to be flip- chip assembled using underfill.
• FIG. 1 illustrates an opto-electronic flip-chip assembly with non- selective underfill, as is typical in the prior art.
• Flip-chip assembly 100 includes a flip chip 110 with an array of solder bumps 120 attached to a substrate 130 using a non-selective underfill material 140.
• Flip chip 110 may include a series of electronic devices, electrical interconnect traces, electrical vias, and an arrangement of flip-chip pads 112.
• Flip chip 110 may also contain one or more opto-electronic devices 164.
• Solder balls or solder bumps 120 are formed on flip-chip pads 112 using metal deposition, metal electroplating, solder ball placement, or other bump-formation processes as currently known in the art. Solder bumps 120 may be positioned against substrate 130 and heated above the eutectic point of the solder to melt them and connect them to substrate 130.
• Substrate 130 contains an array of interconnect traces and substrate pads 132 for electrically connecting the flip chip to the substrate.
• Substrate 130 may also include one or more substrate optical devices 134 corresponding to flip-chip opto-electronic devices 164.
• Substrate 130 may also include electronic components, optical components, and other flip chips.
• Non-selective underfill material 140 provides additional bonding strength for the die attach. Non-selective underfill material 140 also provides stress relief at the solder ball interfaces during temperature excursions of the flip-chip assembly, and provides environmental protection from moisture, particles, and other contamination that may degrade the performance of the flip chip.
• the underfill material may be applied to the flip chip before the reflow step, or applied to the periphery of the flip chip after reflow is completed and then wicked into the region between the surface of the flip chip and the substrate to bond them together and provide protection.
• Non-selective underfill material 140 is also located between flip-chip optoelectronic devices 164 and substrate optical devices 134. This underfill process is not selective, and does not provide an unimpeded optical path between opto-electronic devices on the flip chip and corresponding devices on the substrate for free-space transmission of optical signals.
• non-selective underfill material 140 To transfer optical energy between flip chip 110 and substrate 130, non-selective underfill material 140 must be nominally transparent over the wavelengths of interest and be free of any defects including non-transparent fragments, voids, and other optical deformities. Filler materials incorporated into non-selective underfill material 140 for TCE-matching considerations must not scatter or disperse the transmission of light unduly. Alternatively, the underfill material may be omitted completely, though at the loss of attendant benefits.
• FIG. 2 illustrates one embodiment of an opto-electronic or electromechanical flip-chip assembly with selective underfill, in accordance with the present invention at 200.
• Selective underfill flip-chip assembly 200 includes one or more opto-electronic or electromechanical flip chips 210 containing at least one solder ball or solder bump 220 electrically connected to a substrate or printed wiring board (PWB) 230, and selective underfill material 240 between the bumped surface of flip chip 210 and PWB 230.
• Flip chip 210 may contain a multitude of active components, passive components, or any combination thereof.
• Flip chip 210 may contain electronic components such as resistors, capacitors, and transistors. These components may be integrated onto flip chip 210.
• Flip chip 210 may contain one or more integrated circuits.
• Flip chip 210 may include a set of electrical interconnect traces and flip-chip pads 212.
• Flip chip 210 may contain one or more optical devices in optical or electromechanical portion 260.
• Flip chip 210 may contain one or more opto-electronic or electromechanical devices 264 such as a photodiode, a photo detector, a photodiode array, or a photodetector array.
• Flip chip 210 may contain one or more light-emitting diodes, semiconductor lasers, vertical-cavity surface emitting lasers, edge- emitting lasers, a photo emitter, a light emitter, or a light detector.
• Flip chip 210 may contain one or more passive optical devices such as an optical waveguide, a refractive element such as a microlens or a microlens array, a reflective element such as a mirror, or an optical element. Flip chip 210 may contain any combination of these active and passive elements.
• flip chip 210 may contain one or more electromechanical devices in electromechanical portion 260.
• Flip chip 210 may contain one or more electromechanical devices such as an electromechanical filter, an electromechanical relay, an acoustic emitter, an acoustic detector, a surface acoustic wave device, a bulk acoustic wave device, a thin-film mechanical element, a microfluidic device, or a micro-electro-mechanical device.
• flip chip 210 is a bumped opto-electronic flip chip or a bumped electromechanical flip chip.
• Flip chip 210 may include at least one solder bump or at least one solder ball on the active surface of the flip chip.
• solder balls or solder bumps 220 are typically formed by metal depositions, metal electroplating, solder ball placement, or other bump-formation processes as currently known in the art. Solder balls or solder bumps 220 may be positioned against PWB 230 and heated to melt them and to connect them to PWB 230.
• PWB 230 may contain an array of interconnect traces and substrate pads 232 for electrically connecting flip chip 210 to PWB 230.
• PWB 230 may contain one or more active and passive devices bonded to PWB 230 or formed on PWB 230.
• PWB 230 may be a printed circuit board.
• the printed wiring board may be a single or multi-layer fiberglass FR4 board, an organic circuit board, or a motherboard.
• PWB 230 may be an opto-electronic module, an electromechanical module, a ceramic substrate, a hybrid circuit substrate, a package substrate, or a semiconductor substrate such as a silicon substrate or a compound semiconductor substrate.
• PWB 230 may be a polyimide tape, a flex circuit, a high-density interconnect board, an electromechanical circuit board, or an opto-electronic circuit board.
• An active surface of flip chip 210 may be positioned and secured to PWB 230, and at least one opto-electronic device on the flip chip is optically coupled to an associated device on PWB 230.
• PWB 230 of one embodiment includes one or more substrate optical devices 234 corresponding to flip-chip opto-electronic or electromechanical devices 264.
• Substrate optical device 234 may be a photodiode, a photo detector, a photodiode array, a photodetector array, a light-emitting diode, a semiconductor laser, a vertical-cavity surface emitting laser, an edge-emitting laser, a photo emitter, a light emitter, a light detector, an optical waveguide, a refractive element, a reflective element, an optical element, or any combination thereof.
• a VCSEL laser on flip chip 210 may be optically aligned to a photo detector or a passive optical waveguide on PWB 230.
• PWB 230 may contain apertures and multiple layers with waveguides, prisms, mirrors, and other optical elements.
• Selective underfill material 240 may be located or disposed on a non- optical and non-electromechanical portion 250 of flip chip 210.
• Non-optical and non-electromechanical portion 250 may contain one or more passive or active electronic devices 254.
• Selective underfill material 240 may be omitted from one or more optical or electromechanical portions 260 of flip chip 210.
• One or more optical or electromechanical portions 260 of flip chip 210 may be free of selective underfill material 240 when flip chip 210 is placed on a printed wiring board and heated to electrically connect flip chip 210 to PWB 230.
• Optical or electromechanical portion 260 may include at least one optical or electromechanical devices 264. Not all optical and electromechanical portions 260 of flip chip 210 need to be free of selective underfill material 240, if the optical or electromechanical devices are not negatively impacted by the underfill material or have no corresponding element on PWB 230.
• Selective underfill material 240 may comprise a filled epoxy, such as a one or two part epoxy that contains insulating microspheres to separate flip chip 210 from PWB 230 during die attach processes. Fillers may be added to the selective underfill material to improve thermal expansion characteristics of the underfill material.
• Selective underfill material 240 may include an epoxy, a thermoplastic material, a thermoset material, polyimide, polyurethane, a polymeric material, a filled epoxy, a filled thermoplastic material, a filled thermoset material, filled polyimide, filled polyurethane, a filled polymeric material, or any suitable underfill compound.
• FIG. 3 shows a cross-sectional view of a bumped opto-electronic or electromechanical flip chip with selective underfill, in accordance with one embodiment of the present invention at 300.
• Bumped opto-electronic or electromechanical flip chip with selective underfill 300 may include bumped flip chip 310 with bumps 320, and selective underfill material 340.
• Bumps 320 may be solder bumps or solder balls on an active surface of flip chip 310.
• Bumps 320 may be connected to flip chip 310 at flip-chip pads 312.
• Flip-chip pads 312 may be connected to electrical, electronic, and optical devices on flip chip 310 with one or more on-chip interconnect traces.
• Bumped opto-electronic or electromechanical flip chip with selective underfill 300 often includes a non-optical and non-electromechanical portion 350 and an optical or electromechanical portion 360.
• Non-optical and non- electromechanical portion 350 may include one or more passive or active electronic devices 354.
• Bumped flip chip 310 may include at least one optical or electromechanical device 364.
• Optical portion 360 may include at least one optical or electromechanical device 364.
• Optical device 364 may be a photodiode, a photo detector, a photodiode array, a photodetector array, a light-emitting diode, a semiconductor laser, a vertical-cavity surface emitting laser, an edge-emitting laser, a photo emitter, a light emitter, a light detector, an optical waveguide, a refractive element, a reflective element, an optical element, or any combination thereof.
• Electromechanical device 364 may be an electromechanical filter, an electromechanical relay, an acoustic emitter, an acoustic detector, a surface acoustic wave device, a bulk acoustic wave device, a thin-film mechanical element, a microfluidic device, or a micro- electro-mechanical device.
• Underfill material 340 may be located on non-optical and non- electromechanical portions 350, while optical or electromechanical portions 360 of flip chip 310 are free of underfill material 340.
• Underfill material 340 may include a filled epoxy, such as an epoxy filled with glass or insulating microspheres.
• Underfill material 340 may be an epoxy, a thermoplastic material, a thermoset material, polyimide, polyurethane, a polymeric material, a filled thermoplastic material, a filled thermoset material, filled polyimide, filled polyurethane, a filled polymeric material, or any suitable underfill compound.
• the underfill material may be disposed on non-optical and non- electromechanical portion 350 of flip chip 310.
• Underfill material 340 may be a thickness less than a height of bumps 320. Underfill material 340 may be thicker than one-half of the bump thickness and less than the height of the bumps. Underfill material 340 may be thicker than the height of the bumps, provided that good electrical connection can be made to flip chip 310 when reflowed. Underfill material 340 may be a transparent material, a semi- transparent material, or a non-transparent material, since optical portions of flip chip 310 are free of the material and the non-optical portions of the flip chip are not impacted by transmissivity of the underfill material. Underfill material 340 may provide strain relief for electrically connected flip chip 310. FIG.
• Bumped flip chip 400 includes an opto-electronic or electromechanical flip chip 410, an array of flip-chip bumps 420, and selective underfill material 440.
• Bumped flip chip 400 includes a non-optical and non-electromechanical portion 450 and one or more optical or electromechanical portions 460a, 460b and 460c.
• Non-optical and non-electromechanical portion 450 may include one or more active or passive electronic devices 454.
• Optical or electromechanical portions 460a, 460b and 460c may include one or more optical or electromechanical devices 464.
• Opto-electronic or electromechanical flip chip 410 may include any combination of active and passive electronic and optical devices, such as a photodiode, a photo detector, a photodiode array, a photodetector array, a light-emitting diode, a semiconductor laser, a vertical-cavity surface emitting laser, an edge-emitting laser, a photo emitter, a light emitter, a light detector, an optical waveguide, a refractive element, a reflective element, an optical element, or any combination thereof.
• Opto-electronic flip chip 410 includes at least one solder bump or at least one solder ball on an active surface of the flip chip.
• Electromechanical flip chip 410 may include any combination of active and passive electronic devices, and one or more electromechanical devices such as an electromechanical filter, an electromechanical relay, an acoustic emitter, an acoustic detector, a surface acoustic wave device, a bulk acoustic wave device, a thin-film mechanical element, a microfluidic device, and a micro-electro-mechanical device.
• electromechanical devices such as an electromechanical filter, an electromechanical relay, an acoustic emitter, an acoustic detector, a surface acoustic wave device, a bulk acoustic wave device, a thin-film mechanical element, a microfluidic device, and a micro-electro-mechanical device.
• Flip-chip bumps 420 may be formed on opto-electronic or electromechanical flip chip 410 using deposited metals, electroplated metals, solder ball placement techniques, or any suitable solder ball or solder bump process as is known in the art.
• Underfill material 440 is selectively disposed on non-optical and non- electromechanical portions of opto-electronic or electromechanical flip chip 410.
• Underfill material 440 may be a thickness less than the height of at least one bump.
• Underfill material 440 may cover or partially cover flip-chip bumps 420.
• Underfill material 440 may be transparent, partially transparent, or opaque over the wavelengths of interest.
• Underfill material 440 provides strain relief for the electrically connected flip chip.
• Underfill material 440 typically includes an epoxy, a thermoplastic material, a thermoset material, polyimide, polyurethane, a polymeric material, a filled thermoplastic material, a filled thermoset material, filled polyimide, filled polyurethane, a filled polymeric material, or any suitable underfill compound.
• FIG. 5 shows a block diagram of a method for attaching an opto- electronic or electromechanical flip chip to a printed wiring board, in accordance with one embodiment of the present invention at 500.
• Flip-chip attachment method 500 also referred to as prime chip attach, comprises steps to apply a selective underfill material to a bumped opto-electronic or electromechanical flip chip and to attach the flip chip to a printed wiring board.
• the flip chip includes at least one optical or electromechanical device located in an optical or electromechanical portion of the flip chip.
• the optical device may include a photodiode, a photo detector, a photodiode array, a photodetector array, a light-emitting diode, a semiconductor laser, a vertical- cavity surface emitting laser, an edge-emitting laser, a photo emitter, a light emitter, a light detector, an optical waveguide, a refractive element, a reflective element, an optical element, or any combinations thereof.
• the electromechanical device may include an electromechanical filter, an electromechanical relay, an acoustic emitter, an acoustic detector, a surface acoustic wave device, a bulk acoustic wave device, a thin-film mechanical element, a microfluidic device, or any micro-electro-mechanical device.
• a bumped opto- electronic or electromechanical flip chip is provided.
• a patterned mask is positioned against a bumped surface of the opto-electronic or electromechanical flip chip, as seen at block 510.
• the opto-electronic or electromechanical flip chip typically contains one or more solder bumps or solder balls on the active surface of the flip chip.
• the patterned mask may comprise a fine-mesh screen with one or more barrier features on the screen.
• the barrier features may include features that cover optical and electromechanical portions of the flip chip.
• the patterned mask may include barrier features over the streets when wafer-level underfill is applied.
• the patterned mask may be a stencil with holes and other features punched or formed in a sheet of material such as plastic or metal.
• Material such as gels, suspensions, slurries and viscous liquids may be pressed through the open mask areas to leave a thin coat of material on the underlying substrate.
• An underfill material may be applied to a non-optical and non-electromechanical portion of the flip chip, wherein one or more optical or electromechanical portions of the flip chip are kept free of the underfill material. The underfill material may then be dried and stabilized, partially cured, or otherwise solidified.
• the underfill material may be dispensed through the patterned mask onto one or more non-optical and non-electromechanical portions of the flip chip, as seen at block 520.
• the underfill material may include an epoxy, a thermoplastic material, a thermoset material, polyimide, polyurethane, a polymeric material, a filled thermoplastic material, a filled thermoset material, filled polyimide, filled polyurethane, a filled polymeric material, or any suitable underfill compound.
• the underfill material may be transparent, semi- transparent or non-transparent over the wavelengths of interest.
• the underfill material may be dispensed to a thickness up to the thickness of the bumps on the flip chip.
• the underfill material may be dispensed to a thickness greater than the thickness of the bumps to cover the bumps, provided that the underfill material will soften and allow the bumps to be electrically connected to the printed wiring board during reflow.
• the underfill material may be heat-treated, as seen at block 530.
• the underfill material is heated to flow the underfill material around the solder bumps, while the opto-electronic and electromechanical devices remain free from the underfill material.
• the viscosity of the underfill material may be selected such that the underfill material flows adequately around the bumps, though does not flow into the optical or electromechanical regions of the flip chip.
• the underfill material may be heated to a predefined temperature to drive out solvents and solidify the material though not necessarily cure it.
• Underfill materials based on epoxies and other polymeric materials may be heated to an underfill material staging temperature to dry the underfill such that the underfill is no longer tacky.
• the underfill material may be dried and remain uncured or be partially cured after the heating step.
• the underfill material staging temperature may be between, for example, 80 degrees centigrade and 150 degrees centigrade.
• the heat-treatment step may be done in a controlled environment such as air, nitrogen, or vacuum. Staging temperatures are typically sustained for 30 minutes to over 2 hours.
• the underfill material may be applied to the non-optical and non-electromechanical portions of the flip chip using a die-cut film, a laminate of an underfill material and a backing layer, or other sheet form of patterned underfill material.
• the die-cut film or patterned underfill film may be aligned to the bumped flip chip, positioned against the bumped surface of the flip chip, and pressed onto the flip chip while heating to adhere the underfill material to the flip chip.
• the backing layer may then be removed.
• the region between the patterned underfill film may be pumped out to remove air between the patterned underfill film and the flip chip, then the underfill material is heated with the flip chip to adhere the selective underfill to the flip chip.
• the flip chip may be positioned on a printed wiring board so that an optical device on the flip chip aligns to a corresponding optical device on the printed wiring board, as seen at block 540.
• the printed wiring board may be a single layer or multi-layer FR4 board, an organic circuit board, a motherboard, an opto-electronic module, an electromechanical module, a ceramic substrate, a hybrid circuit substrate, a package substrate, a semiconductor substrate, a polyimide tape, a flex circuit, a high-density interconnect board, an electromechanical circuit board, or an opto-electronic circuit board.
• the flip-chip bumps may be heated to or above a reflow temperature of the bumped opto-electronic or electromechanical flip chip to electrically and mechanically connect the flip chip to the printed wiring board, as seen at block 550.
• a reflow temperature of the bumped opto-electronic or electromechanical flip chip to electrically and mechanically connect the flip chip to the printed wiring board.
• the solder bumps will liquefy and become soldered to the printed wiring board.
• the heat source may be removed and the flip-chip assembly cooled to room temperature.
• the reflow temperature for example, may be between 183 degrees centigrade and 220 degrees centigrade for lead-tin solder bumps.
• the reflow temperature may be between 220 degrees centigrade and 250 degrees centigrade for lead-free or low lead-content bumps.
• the reflow temperature may extend as low as 160 degrees centigrade or lower for the case of low- temperature solders based on indium or other materials.
• the devices on the flip chip become electrically and mechanically connected to the printed wiring board after the heating step, as seen at block 560.
• the optical and electromechanical portions of the flip chip remain free of the underfill material.
• the underfill material provides strain relief for the electrically connected flip chip.
• An encapsulant or other suitable protective material may subsequently encase the flip-chip assembly.
• a post-cure step may be incorporated.
• the selective underfill may be heated to an underfill post-cure temperature of between, for example, 100 degrees centigrade and 150 degrees centigrade, for a time on the order of 15 to 30 minutes.
• FIG. 6 shows a block diagram of a selective underfill process, in accordance with one embodiment of the present invention at 600.
• Selective underfill process 600 also referred to as wafer-applied underfill, comprises steps to selectively dispense underfill material on a provided bumped semiconductor wafer or a bumped flip chip.
• the bumped semiconductor wafer may contain an array of bumped flip chips.
• the semiconductor wafer includes at least one solder bump or solder ball and at least one optoelectronic or electromechanical device.
• the semiconductor wafer may comprise a silicon wafer with at least one opto-electronic or electromechanical device.
• the semiconductor wafer may comprise gallium arsenide, gallium nitride, indium phosphide, or other suitable opto-electronic semiconductor material.
• a patterned mask may be aligned to the bumped semiconductor wafer or flip chip, as seen at block 610.
• the underfill material may be dispensed selectively onto the bumped semiconductor wafer through areas of the mask not blocked by any barrier features on the mask.
• the patterned mask includes at least one barrier feature corresponding to one or more opto-electronic or electromechanical devices.
• the underfill material can be dispensed through the patterned mask onto the bumped semiconductor wafer, where the opto-electronic and electromechanical devices remain free from the underfill material as seen at block 620. With this method, other wafer-level features such as dicing streets can also be kept free of underfill material.
• the underfill material is typically heated to dry the underfill material, as seen at block 630.
• the underfill material may be heated to or above an underfill material staging temperature.
• the underfill material staging temperature is typically between 80 degrees centigrade and 150 degrees centigrade. Drying times may be between two minutes and twenty minutes or longer.
• the underfill material may partially cure during this step.
• the underfill material is heated to flow the underfill material around the solder bumps in non-optical and non- electromechanical areas during the staging cycle or during a partial curing cycle to flow the material around the solder bumps, while the opto-electronic devices remain free from the underfill material, as seen at block 640.
• the underfill material may be softened and flowed to provide good adhesion and coverage of the bumps.
• the cycles may be greater than ten minutes to over two hours at a temperature up to 150 degrees centigrade or higher in an air, nitrogen, or other controlled environment.
• the bumped semiconductor wafer may be diced to form individual flip chips, as seen at block 650.
• the flip chips have bumps and selective underfill material, and may be attached to printed wiring boards and other substrates in flip-chip assemblies.
• FIG. 7 shows a block diagram of a selective underfill process, in accordance with another embodiment of the present invention at 700.
• Selective underfill process 700 also referred to as wafer-applied underfill, comprises steps to selectively dispense underfill material on a provided bumped semiconductor wafer or a bumped flip chip, using a patterned underfill film.
• the bumped semiconductor wafer includes at least one of an opto-electronic device or an electromechanical device, and at least one solder bump.
• the patterned underfill film may be a die-cut film or a laminate including an underfill material and a release or backing layer.
• the patterned underfill film includes a thin layer of underfill material such as an epoxy, a thermoplastic material, a thermoset material, polyimide, polyurethane, a polymeric material, a filled epoxy, a filled thermoplastic material, a filled thermoset material, filled polyimide, filled polyurethane, a filled polymeric material, or any suitable underfill compound.
• the backing layer may be a transparent plastic, mylar or acetate sheet used to support the underfill material.
• Windows, apertures, streets and other features may be formed in the underfill layer.
• the underfill material may be cut or punched with a die to form prescribed shapes.
• the underfill material may be selectively ablated with a laser, or fashioned into the desired patterns using any suitable formation technique.
• the patterned underfill film is aligned to the surface of a bumped semiconductor wafer, as shown at block 710. At least one open feature in the patterned underfill material is aligned to at least one of an opto-electronic device or an electromechanical device on the bumped wafer.
• the patterned underfill film is laminated to the bumped semiconductor wafer, as seen at block 720.
• the patterned underfill film may be laminated to the bumped semiconductor wafer by pressing the patterned underfill film against the bumped semiconductor wafer when the patterned underfill film and the bumped semiconductor wafer are at a lamination temperature.
• the lamination temperature may be between 60 degrees centigrade and 100 degrees centigrade, for example.
• the patterned underfill film may be pressed with a hot roller, with a press, or with any suitable pressing mechanism.
• the patterned underfill film may be laminated by pumping out the region between the patterned underfill film and the bumped semiconductor wafer to remove trapped air and to firmly hold the patterned underfill film against the bumped semiconductor wafer.
• the bumped semiconductor wafer and the patterned underfill film may be heated to a lamination temperature such as a temperature between 60 degrees centigrade and 100 degrees centigrade.
• the backing layer may be removed, as seen at block 730.
• the backing layer may be peeled back or otherwise separated from the underfill material and the bumped semiconductor wafer.
• the underfill material remains laminated to the bumped semiconductor wafer, and the opto-electronic devices or electromechanical devices are free from the underfill material.
• the underfill material is flowed around bumps in non-optical and non- electromechanical areas on the bumped semiconductor wafer, as seen at block 740.
• the underfill material may be heated to a temperature such that the underfill material flows around the bumps, though does not flow into the opto-electronic or electromechanical devices.
• the opto-electronic devices or electromechanical devices remain free from the underfill material.
• the bumped semiconductor wafer with the underfill material may be diced to form individual flip chips, as seen at block 750.
• the flip chips have bumps and selective underfill material, and may be attached to printed wiring boards and other substrates in flip-chip assemblies.

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• Wire Bonding (AREA)
• Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
• Led Device Packages (AREA)
• Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
• Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

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• 2002
  • 2002-12-23 US US10/328,326 patent/US6800946B2/en not_active Expired - Lifetime
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  • 2003-12-11 WO PCT/US2003/039425 patent/WO2004061934A1/en not_active Ceased
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