US20170146741A1 - Optical device with precoated underfill - Google Patents

Optical device with precoated underfill Download PDF

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Publication number
US20170146741A1
US20170146741A1 US15/287,582 US201615287582A US2017146741A1 US 20170146741 A1 US20170146741 A1 US 20170146741A1 US 201615287582 A US201615287582 A US 201615287582A US 2017146741 A1 US2017146741 A1 US 2017146741A1
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chip
waveguide module
waveguide
underfill material
underfill
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US15/287,582
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Akihiro Horibe
Masao Tokunari
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International Business Machines Corp
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International Business Machines Corp
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Priority to US14/947,855 priority Critical patent/US9721812B2/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US15/287,582 priority patent/US20170146741A1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HORIBE, AKIHIRO, TOKUNARI, MASAO
Publication of US20170146741A1 publication Critical patent/US20170146741A1/en
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    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
    • G02B6/00Light guides
    • G02B6/10Light guides of the optical waveguide type
    • G02B6/12Light guides of the optical waveguide type of the integrated circuit kind
    • G02B6/13Integrated optical circuits characterised by the manufacturing method
    • G02B6/138Integrated optical circuits characterised by the manufacturing method by using polymerisation
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
    • G02B6/00Light guides
    • G02B6/10Light guides of the optical waveguide type
    • G02B6/12Light guides of the optical waveguide type of the integrated circuit kind
    • G02B6/12004Combinations of two or more optical elements
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
    • G02B6/00Light guides
    • G02B6/24Coupling light guides
    • G02B6/42Coupling light guides with opto-electronic elements
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
    • G02B6/00Light guides
    • G02B6/24Coupling light guides
    • G02B6/42Coupling light guides with opto-electronic elements
    • G02B6/4201Packages, e.g. shape, construction, internal or external details
    • G02B6/4204Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms
    • G02B6/4214Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
    • G02B6/00Light guides
    • G02B6/10Light guides of the optical waveguide type
    • G02B6/12Light guides of the optical waveguide type of the integrated circuit kind
    • G02B2006/12083Constructional arrangements
    • G02B2006/12104Mirror; Reflectors or the like
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
    • G02B6/00Light guides
    • G02B6/24Coupling light guides
    • G02B6/42Coupling light guides with opto-electronic elements
    • G02B6/4201Packages, e.g. shape, construction, internal or external details
    • G02B6/4219Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4228Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
    • G02B6/4232Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using the surface tension of fluid solder to align the elements, e.g. solder bump techniques
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/03452Chemical vapour deposition [CVD], e.g. laser CVD
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12043Photo diode

Abstract

A method for fabricating an optical multi-chip module (MCM) includes temporarily curing an underfill material on a chip including an optical device to prevent flow of the underfill material. The chip is flip-chip mounted on a waveguide module having a mirror for directing light to or from the chip, wherein the underfill material is disposed between the chip and the waveguide module. The underfill material is cured to adhere the chip to the waveguide module.

Description

    BACKGROUND
  • Technical Field
  • The present invention relates to optical devices, and more particularly to optical device integration using an underfill material to eliminate losses between a photonics device and an optical component.
  • Description of the Related Art
  • An optical multi-chip module (MCM) includes optical waveguides on an organic substrate where optical devices such as vertical cavity surface emitting laser (VCSEL) or photodiode (PD) chips are mounted. The light from/to the device is coupled with the optical waveguides via 45-degree mirrors, where total internal reflection (TIR) mirrors manufactured by laser ablation techniques are employed for high channel density applications.
  • The VCSEL/PD chips are encapsulated by an underfill when placed on the organic substrate. During production, the underfill material enters mirror cavities located on a same side as the chips so that the TIR mirrors do not function properly. Loss can also be caused by an inclination of the VCSEL/PD chips when electrodes are located slightly off a chip center and cannot be well-controlled when they are mounted.
  • SUMMARY
  • A method for fabricating an optical multi-chip module (MCM) includes temporarily curing an underfill material on a chip including an optical device to prevent flow of the underfill material. The chip is flip-chip mounted on a waveguide module having a mirror for directing light to or from the chip, wherein the underfill material is disposed between the chip and the waveguide module. The underfill material is cured to adhere the chip to the waveguide module.
  • Another method for fabricating an optical multi-chip module (MCM) includes depositing an underfill material over a wafer having a plurality of chips with raised electrodes, the plurality of chips including optical devices; removing the underfill material from the raised electrodes; temporarily curing the underfill material; dicing the wafer to separate the plurality of chips; flip-chip mounting a chip of the plurality of chips on a waveguide module having a mirror for directing light to or from the chip, wherein the underfill material is disposed between the chip and the waveguide module; and curing the underfill material to adhere the chip to the waveguide module.
  • An optical multi-chip module (MCM) includes a waveguide module having a cavity with a mirror. The mirror is configured to direct light into or from a waveguide formed in the waveguide module. A chip flip-chip is mounted on the waveguide module to have a light input or output formed on the chip aligned with the mirror. A reflowable underfill material is disposed between the chip and the waveguide module to adhere the chip to the waveguide module without filling the cavity.
  • These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:
  • FIG. 1 is a side view of a wafer covered by an underfill material and having optical devices, such as, vertical cavity surface emitting laser (VCSEL) or photodiode (PD) chips formed therein with raised electrodes in accordance with the present principles;
  • FIG. 2 is a side view of the wafer of FIG. 1 showing the underfill material of the wafer being processed with a mask during a lithography process to remove the underfill material from the raised electrodes in accordance with the present principles;
  • FIG. 3 is a side view of the wafer of FIG. 2 showing the underfill material removed from the raised electrodes and temporarily cured in accordance with the present principles;
  • FIG. 4 is a side view of a chip diced from the wafer of FIG. 3 in accordance with the present principles;
  • FIG. 5 is a cross-sectional view of an optical multi-chip module (MCM) including a cured underfill material adhering the chip of FIG. 4 to a waveguide module without interfering with a light cavity in the waveguide module in accordance with the present principles; and
  • FIG. 6 is a block/flow diagram showing a method for forming an optical multi-chip module in accordance with illustrative embodiments.
  • DETAILED DESCRIPTION
  • In accordance with the present principles, structures and methods are provided for optical devices that are employed with infrared-transparent photosensitive thermal-curing underfill. The underfill may include, e.g., cyclotene resin, and may be pre-coated on optical chips or provided on optical waveguide-integrated organic substrates with total internal reflection (TIR) mirrors. Since the underfill is pre-coated and semi-cured in advance, there is no danger of filling mirror cavities. In addition, an optical path between the optical device and a waveguide is still filled with the underfill to eliminate any air gaps. The TIR mirror cavities remain open on the waveguides at a side where the devices are mounted, and are not filled with the underfill to maintain low-loss optical coupling. Use of transparent underfill fills between vertical cavity surface emitting laser (VCSEL) or photodiode (PD) (VCSEL/PD) chips and the waveguide, still results in loss reduction by eliminating air interface reflection in the gap space. In accordance with the present principles more precise control of the underfill area is provided.
  • A distance between the devices and the waveguides is minimized for low-loss optical coupling by removing the underfill at an electrode area of the device and using through-waveguide-vias instead of inserting flexible printed circuits between those two components for electric connection of the devices. The underfill thickness is also minimized, and no lens is employed on the optical device to further reduce cost.
  • It is to be understood that the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps may be varied within the scope of the present invention.
  • It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
  • The present embodiments may include a design for an integrated circuit chip, which may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
  • Methods as described herein may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as an organic carrier or a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
  • Reference in the specification to “one embodiment” or “an embodiment” of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
  • It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.
  • Referring now to the drawings in which like numerals represent the same or similar elements and initially to FIG. 1, a wafer 10 is shown for processing in accordance with one illustrative embodiment. The wafer 10 includes a plurality of chips 15 formed thereon. The chips 15 may include lasers, photodiodes or other light emitting or receiving devices, herein referred to as optical devices. In one embodiment, the chips 15 include vertical cavity surface emitting laser (VCSEL) chips or photodiode (PD) chips. The chips 15 include one or more pads or contacts 14 for making electrical connections to the chip 15. The contacts 14 may be deposited on the wafer 10 and patterned to shape the contacts 14. The deposition of the contacts 14 may include any process for forming metal including, e.g., sputtering, evaporation, chemical vapor deposition, etc. The contacts 14 may include a solder ball 16 formed thereon for making an electrical connection to other components as will be described. The contacts 14 and solder balls 16 will be collectively referred to as electrodes 25.
  • An underfill material or underfill 18 is formed over the wafer 10. The underfill 18 may include, e.g., cyclotene resin. The underfill 18 may be applied using a spin on process, although other processes may be employed to apply the underfill 18 on the wafer. The underfill thickness is adjustable by controlling a rotation speed of a spin coater. The thickness of the underfill 18 is provided in accordance with a gap distance needed between a chip and a waveguide.
  • Referring to FIG. 2, after forming the underfill 18, a soft bake process may be performed to harden the underfill 18. In one embodiment, the wafer 10 with the underfill 18 is baked at a temperature of between about 60 degrees C. and about 80 degrees C. for about 90 seconds. The underfill 18 over the electrodes 25 is removed by a photolithography process. The photolithography process may include positioning a mask 20 over the wafer 10, exposing the underfill 18 to light in accordance with the mask 20 to cause cross-linking, and developing the underfill layer 18 to remove portions of the underfill 18 over the electrodes 25.
  • Referring to FIG. 3, the underfill 18 is subjected to a temporary hardening process by subjecting the underfill 18 to a reflow at between 100 degrees C. to about 140 degrees C., and preferably about 125 degree C. for about 3 minutes. The underfill 18 is allowed to cool.
  • Referring to FIG. 4, the wafer 10 is diced into individual chips 40. Each chip 40 includes its own electrodes 25, which will be employed in making electrical connections to other components.
  • Referring to FIG. 5, a flip-chip assembly is performed to couple the chip 40 to a waveguide 44 formed on a substrate 42 to form an optical multi-chip module (MCM) 100. The substrate 42 may include an organic material. The waveguide 44 is formed between cladding layers 48. A contact connection 50 receives the electrode 25 therein and includes conductive material to create electrical connections to the chip 40. A light emitting or receiving region 52 on the chip 40 is aligned with a mirror 45. The mirror 45 such as a total internal reflection (TIR) mirror is employed to redirect light into the waveguide 44 from the light emitting or receiving region 52 of the chip 40. A cavity 46 for the mirror 45 may be formed by laser ablation to be at a 45 degree angle relative to the surface of the chip 40.
  • There are a number of reasons and advantages to having the mirror 45 on the mounting side of the chip 40. For example, the mirror 45 is provided in close proximity to the light emission position of the chip 40. Also, the chip 40 may be employed to cover the cavity 46 for the mirror 45.
  • Once the chip 40 is positioned, a curing process is performed, which may include adhesion of the underfill 18 by a reflow process. The reflow process may include subjecting the underfill to a temperature of between about 130 degrees C. to about 160 degrees C., preferably about 150 degrees C. for about 5 minutes. Then, a hardening process is performed at a temperature of between about 200 degrees C. and about 220 degrees C., preferably about 210 degrees C. for about 40 minutes. Solder bonding of the electrode 25 to the contact connection is performed by a 240 degrees C. to about 260 degrees C. solder reflow process.
  • By pre-coating the chip 40 with the underfill 18, the underfill 18 remains well-controlled. A thickness of the underfill 18 is controlled at its deposition and forms a highly controlled gap dimension 54. In addition, reflowing the underfill 18 does not permit the underfill material 18 to flow and fill in the cavity 46. Instead, the underfill 18 is softened and provides adhesion without the ill-effects of conventional devices, which fill the cavity and result in optical losses.
  • Since the underfill is pre-coated and cured in advance, there is no danger of filling mirror cavities. Air gaps between the chip 40 and the top cladding layer 48 are virtually eliminated between the chip 40 and the mirror 45. The present principles provide a low cost solution with a yield improvement for optical MCM manufacturing by preventing underfill 18 from entering TIR mirror cavities 46. The pre-coating with underfill 18 is concurrently provided on multiple optical devices by wafer-level processing.
  • The optical MCM 100 provides low power consumption (e.g., optical coupling loss reduction) since distance between the chip 40 and the waveguide 44 is reduced by underfill thickness control. In one embodiment, gap distances 54 of less than about 5 microns are provided. In addition, by including a uniform thickness of underfill 18, inclination of the chip 40 relative a waveguide module 60 is reduced or eliminated. In one embodiment, the chip 40 and waveguide cladding 48 surfaces are stuck together flat with the underfill 18 acting as an adhesive. This also improves the interfaces (and therefore light transmission) through the underfill 18.
  • While one embodiment depicts applying the underfill material to a wafer, other embodiments may apply the underfill material directly to a chip instead of the wafer. Processing is similar but employs one or more chips instead of the wafer.
  • Experiment: Underfill (18) was dispensed and cured on polymer waveguides for confirming adhesion and evaluating optical properties. In one process, a pre-coat of underfill on a glass substrate by a spin process (rotational speed of spin coater being 3000 rotations per minute (rpm)) was performed. A soft bake at 70 degrees C. for 90 seconds and a temporary cure at 125 degrees C. for 3 minutes were performed. Then, a waveguide-integrated substrate on glass was attached and fixed using a clip. An underfill adhesion includes 150 degrees C. for 5 minutes, and a cure at 210 degrees C. for 40 minutes.
  • Insertion loss measurement results were taken for the following two configurations. The first configuration included a waveguide and a glass substrate with index matching fluid (IMF) dispensed between a waveguide and a glass. The loss measured by a photodetector (1 cm) was −0.46 dB. The second configuration included a waveguide with underfill in accordance with the present principles. The loss measured by a photodetector (1 cm) was −0.40 dB with no insertion loss degradation after underfill cure (the 0.06 dB improvement is within the measurement error range). This means that no air layer existed between the waveguide and underfill.
  • In addition, the present principles do not require a lens or flexible printed circuit (FPC) between the chip 40 and the cavity 46. While no lens or FPC is needed, these components may be employed in some embodiments depending on the application. However, these components add costs and complexity to the manufacturing process.
  • Referring to FIG. 6, a method for fabricating an optical multi-chip module (MCM) is shown in accordance with illustrative embodiments. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
  • In block 202, an underfill material is applied to a wafer or chip. This may include a spin-on process or other deposition process. The application of the underfill material is controlled to control a gap distance. The wafer includes chips. The chip or chips include optical devices, such as photodiodes and/or lasers. The underfill material includes a semi-curable and reflowable resin. Semi-curable refers to a material that is stable being partially (temporarily or semi-) cured and then can be fully cured at a later point. Reflowable refers to the material as being capable of melting and re-solidifying. In one embodiment, the underfill material includes a cyclotene resin.
  • In block 204, a soft bake may be performed to provide some structure to the underfill material. The soft bake may include, e.g., heating at 70 degrees C. for about 90 seconds. In block 206, the underfill material may be removed from raised electrodes formed on the wafer or chip. This may include a lithography process to expose the underfill material through a mask and remove/develop uncross-linked portions to expose the raised electrodes.
  • In block 208, the underfill material is temporarily cured on the wafer or chip to prevent flow of the underfill material. Temporary curing the underfill material may include hardening the underfill material at between 100 degrees C. to about 140 degrees C.
  • In block 210, if a wafer was employed, the wafer is diced or separated into chips. In block 212, the chip is flip-chip mounted on a waveguide module. The light emitting or receiving chip is aligned with a mirror for directing light from/to the chip. The underfill material is disposed between the chip and the waveguide module. Since the chip is pre-coated with a solid or hardened underfill material, the underfill material does not interfere with a cavity in the waveguide module by flowing into the cavity and causing light attenuation. The cavity may include a mirror and a waveguide depending on the design.
  • In block 214, the underfill material is fully cured to adhere the chip to the waveguide module. The full cure may include reflowing the underfill material at a temperature of between about 130 degrees C. to about 160 degrees C. to provide adhesion in block 216, and hardening the underfill material at a temperature of between about 200 degrees C. and about 220 degrees C. in block 218.
  • In block 220, solder joints are reflowed to make solder connections between the light emitting or receiving chip and the waveguide module. In block 222, processing may continue to complete the device/module.
  • Having described preferred embodiments for optical device with precoated underfill (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.

Claims (13)

1. An optical multi-chip module (MCM), comprising:
a waveguide module having a cavity with a mirror, the mirror being configured to direct light into or from a waveguide formed in the waveguide module;
a chip flip-chip mounted on the waveguide module to have a light input or output formed on the chip aligned with the mirror; and
a reflowable underfill material disposed between the chip and the waveguide module to adhere the chip to the waveguide module without filling the cavity.
2. The MCM as recited in claim 1, wherein the underfill material includes a cyclotene resin.
3. The MCM as recited in claim 1, wherein electrodes on the chip are soldered to contacts on the waveguide module.
4. The MCM as recited in claim 1, wherein the underfill material forms a gap distance between the chip and the waveguide module which is provided by a solid form of the underfill material before flip-chip mounting the chip on the waveguide module.
5. The MCM as recited in claim 1, wherein the underfill material includes a semi-curable and reflowable resin.
6. An optical multi-chip module (MCM), comprising:
a waveguide module having a cavity with a mirror, the mirror being configured to direct light into or from a waveguide formed in the waveguide module;
a chip flip-chip mounted on the waveguide module to have a light input or output formed on the chip aligned with the mirror; and
a reflowable underfill material disposed between the chip and the waveguide module to adhere the chip to the waveguide module without filling the cavity; and
one or more electrodes on the chip soldered to contacts on the waveguide module.
7. The MCM as recited in claim 6, wherein the underfill material includes a cyclotene resin.
8. The MCM as recited in claim 6, wherein the underfill material forms a gap distance between the chip and the waveguide module which is provided by a solid form of the underfill material before flip-chip mounting the chip on the waveguide module.
9. The MCM as recited in claim 6, wherein the underfill material includes a semi-curable and reflowable resin.
10. An optical multi-chip module (MCM), comprising:
a waveguide module having a cavity with a mirror;
a chip flip-chip mounted on the waveguide module to have a light input or output formed on the chip aligned with the mirror; and
a reflowable cyclotene resin disposed between the chip and the waveguide module to adhere the chip to the waveguide module without filling the cavity.
11. The MCM as recited in claim 10, wherein the mirror being configured to direct light into or from a waveguide formed in the waveguide module.
12. The MCM as recited in claim 10, wherein electrodes on the chip are soldered to contacts on the waveguide module.
13. The MCM as recited in claim 10, wherein the cyclotene resin forms a gap distance between the chip and the waveguide module which is provided by a solid form of the cyclotene resin before flip-chip mounting the chip on the waveguide module.
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