KR20040102052A - 다중-두께 매립 산화물층 위에 형성된 반도체 디바이스 및그 제조 방법 - Google Patents

다중-두께 매립 산화물층 위에 형성된 반도체 디바이스 및그 제조 방법 Download PDF

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Publication number
KR20040102052A
KR20040102052A KR10-2004-7015051A KR20047015051A KR20040102052A KR 20040102052 A KR20040102052 A KR 20040102052A KR 20047015051 A KR20047015051 A KR 20047015051A KR 20040102052 A KR20040102052 A KR 20040102052A
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KR
South Korea
Prior art keywords
substrate
thickness
semiconductor device
buried oxide
oxide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR10-2004-7015051A
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English (en)
Korean (ko)
Inventor
푸셀리어마크비.
리스터즈데릭제이.
웨이앤디씨.
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
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Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20040102052A publication Critical patent/KR20040102052A/ko
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H10P30/209—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/225—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials

Landscapes

  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR10-2004-7015051A 2002-03-28 2002-12-17 다중-두께 매립 산화물층 위에 형성된 반도체 디바이스 및그 제조 방법 Ceased KR20040102052A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/109,096 2002-03-28
US10/109,096 US6737332B1 (en) 2002-03-28 2002-03-28 Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same
PCT/US2002/040213 WO2003083934A1 (en) 2002-03-28 2002-12-17 Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same

Publications (1)

Publication Number Publication Date
KR20040102052A true KR20040102052A (ko) 2004-12-03

Family

ID=28673615

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2004-7015051A Ceased KR20040102052A (ko) 2002-03-28 2002-12-17 다중-두께 매립 산화물층 위에 형성된 반도체 디바이스 및그 제조 방법

Country Status (8)

Country Link
US (2) US6737332B1 (https=)
EP (1) EP1490900A1 (https=)
JP (1) JP2005522034A (https=)
KR (1) KR20040102052A (https=)
CN (1) CN1310306C (https=)
AU (1) AU2002357862A1 (https=)
TW (1) TWI286821B (https=)
WO (1) WO2003083934A1 (https=)

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KR100724199B1 (ko) * 2005-12-28 2007-05-31 동부일렉트로닉스 주식회사 에스오아이 소자의 섀로우 트렌치 분리막 형성 방법
WO2010080277A1 (en) * 2008-12-18 2010-07-15 Micron Technology, Inc. Method and structure for integrating capacitor-less memory cell with logic
US7785936B2 (en) 2008-07-29 2010-08-31 Hynix Semiconductor Inc. Method for repair of semiconductor device
KR20150053703A (ko) * 2013-11-08 2015-05-18 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 다수의 반도체 디바이스층을 갖는 반도체 구조체를 위한 시스템 및 방법
KR20180061389A (ko) * 2015-10-23 2018-06-07 어플라이드 머티어리얼스, 인코포레이티드 진보된 cmp 및 리세스 플로우를 위한 갭필 필름 수정

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US8450806B2 (en) * 2004-03-31 2013-05-28 International Business Machines Corporation Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby
US7382023B2 (en) * 2004-04-28 2008-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Fully depleted SOI multiple threshold voltage application
US7129138B1 (en) * 2005-04-14 2006-10-31 International Business Machines Corporation Methods of implementing and enhanced silicon-on-insulator (SOI) box structures
JP2006310661A (ja) * 2005-04-28 2006-11-09 Toshiba Corp 半導体基板および製造方法
JP4797495B2 (ja) * 2005-08-02 2011-10-19 セイコーエプソン株式会社 半導体装置の製造方法
US20070099372A1 (en) * 2005-10-31 2007-05-03 Sailesh Chittipeddi Device having active regions of different depths
US8278731B2 (en) * 2007-11-20 2012-10-02 Denso Corporation Semiconductor device having SOI substrate and method for manufacturing the same
US8074897B2 (en) 2008-10-09 2011-12-13 Rain Bird Corporation Sprinkler with variable arc and flow rate
US8695900B2 (en) * 2009-05-29 2014-04-15 Rain Bird Corporation Sprinkler with variable arc and flow rate and method
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JP2011082443A (ja) * 2009-10-09 2011-04-21 Sumco Corp エピタキシャルウェーハおよびその製造方法
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CN102148183B (zh) * 2011-03-10 2015-04-29 上海华虹宏力半导体制造有限公司 具有阶梯型氧化埋层的soi的形成方法
US8507989B2 (en) * 2011-05-16 2013-08-13 International Business Machine Corporation Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance
CN102244029A (zh) * 2011-06-28 2011-11-16 上海宏力半导体制造有限公司 绝缘体上的硅衬底制作工艺及绝缘体上的硅器件制作工艺
CN102244080A (zh) * 2011-06-28 2011-11-16 上海宏力半导体制造有限公司 绝缘体上的硅衬底结构及器件
CN102339784B (zh) * 2011-09-28 2015-02-04 上海华虹宏力半导体制造有限公司 具有阶梯型氧化埋层的soi结构的制作方法
CN102354678B (zh) * 2011-09-28 2015-03-18 上海华虹宏力半导体制造有限公司 具有阶梯型氧化埋层的soi结构
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CN103311301B (zh) * 2013-05-09 2016-06-29 北京大学 一种抑制辐射引起背栅泄漏电流的soi器件及其制备方法
CN105097711B (zh) * 2014-05-04 2018-03-30 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US10204909B2 (en) * 2015-12-22 2019-02-12 Varian Semiconductor Equipment Associates, Inc. Non-uniform gate oxide thickness for DRAM device
US10322423B2 (en) 2016-11-22 2019-06-18 Rain Bird Corporation Rotary nozzle
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Publication number Priority date Publication date Assignee Title
KR100724199B1 (ko) * 2005-12-28 2007-05-31 동부일렉트로닉스 주식회사 에스오아이 소자의 섀로우 트렌치 분리막 형성 방법
US7785936B2 (en) 2008-07-29 2010-08-31 Hynix Semiconductor Inc. Method for repair of semiconductor device
KR101024763B1 (ko) * 2008-07-29 2011-03-24 주식회사 하이닉스반도체 반도체 소자의 리페어 방법
WO2010080277A1 (en) * 2008-12-18 2010-07-15 Micron Technology, Inc. Method and structure for integrating capacitor-less memory cell with logic
US8278167B2 (en) 2008-12-18 2012-10-02 Micron Technology, Inc. Method and structure for integrating capacitor-less memory cell with logic
US8704286B2 (en) 2008-12-18 2014-04-22 Micron Technology, Inc. Method and structure for integrating capacitor-less memory cell with logic
US9129848B2 (en) 2008-12-18 2015-09-08 Micron Technology, Inc. Method and structure for integrating capacitor-less memory cell with logic
KR20150053703A (ko) * 2013-11-08 2015-05-18 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 다수의 반도체 디바이스층을 갖는 반도체 구조체를 위한 시스템 및 방법
US10128269B2 (en) 2013-11-08 2018-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Systems and methods for a semiconductor structure having multiple semiconductor-device layers
US10734411B2 (en) 2013-11-08 2020-08-04 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for a semiconductor structure having multiple semiconductor-device layers
US12087777B2 (en) 2013-11-08 2024-09-10 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for a semiconductor structure having multiple semiconductor-device layers
KR20180061389A (ko) * 2015-10-23 2018-06-07 어플라이드 머티어리얼스, 인코포레이티드 진보된 cmp 및 리세스 플로우를 위한 갭필 필름 수정

Also Published As

Publication number Publication date
AU2002357862A1 (en) 2003-10-13
JP2005522034A (ja) 2005-07-21
CN1310306C (zh) 2007-04-11
TW200307346A (en) 2003-12-01
WO2003083934A1 (en) 2003-10-09
TWI286821B (en) 2007-09-11
US20040219761A1 (en) 2004-11-04
EP1490900A1 (en) 2004-12-29
CN1623226A (zh) 2005-06-01
US6737332B1 (en) 2004-05-18

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