KR20040048985A - 기판에 상호접속을 갖는 집적회로 및 이를 위한 방법 - Google Patents

기판에 상호접속을 갖는 집적회로 및 이를 위한 방법 Download PDF

Info

Publication number
KR20040048985A
KR20040048985A KR10-2004-7006013A KR20047006013A KR20040048985A KR 20040048985 A KR20040048985 A KR 20040048985A KR 20047006013 A KR20047006013 A KR 20047006013A KR 20040048985 A KR20040048985 A KR 20040048985A
Authority
KR
South Korea
Prior art keywords
conductive
region
dielectric
doped
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR10-2004-7006013A
Other languages
English (en)
Korean (ko)
Inventor
더글라스 엠. 레벌
Original Assignee
모토로라 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 모토로라 인코포레이티드 filed Critical 모토로라 인코포레이티드
Publication of KR20040048985A publication Critical patent/KR20040048985A/ko
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
KR10-2004-7006013A 2001-10-22 2002-09-27 기판에 상호접속을 갖는 집적회로 및 이를 위한 방법 Ceased KR20040048985A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/986,232 2001-10-22
US09/986,232 US6555915B1 (en) 2001-10-22 2001-10-22 Integrated circuit having interconnect to a substrate and method therefor
PCT/US2002/030337 WO2003036702A2 (en) 2001-10-22 2002-09-27 Integrated circuit having interconnect to a substrate and method therefor

Publications (1)

Publication Number Publication Date
KR20040048985A true KR20040048985A (ko) 2004-06-10

Family

ID=25532216

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2004-7006013A Ceased KR20040048985A (ko) 2001-10-22 2002-09-27 기판에 상호접속을 갖는 집적회로 및 이를 위한 방법

Country Status (7)

Country Link
US (1) US6555915B1 (enExample)
EP (1) EP1479101A2 (enExample)
JP (1) JP2006500759A (enExample)
KR (1) KR20040048985A (enExample)
CN (1) CN1326210C (enExample)
AU (1) AU2002327714A1 (enExample)
WO (1) WO2003036702A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100825466B1 (ko) * 2004-08-06 2008-04-28 오스트리아마이크로시스템즈 아게 고전압 ｎｍｏｓ 트랜지스터 및 그것의 제조 방법

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003031801A (ja) * 2001-07-16 2003-01-31 Oki Electric Ind Co Ltd 電界効果型トランジスタの製造方法
US20040121524A1 (en) * 2002-12-20 2004-06-24 Micron Technology, Inc. Apparatus and method for controlling diffusion
US7297617B2 (en) * 2003-04-22 2007-11-20 Micron Technology, Inc. Method for controlling diffusion in semiconductor regions
US7654221B2 (en) * 2003-10-06 2010-02-02 Applied Materials, Inc. Apparatus for electroless deposition of metals onto semiconductor substrates
US7297605B2 (en) * 2004-05-10 2007-11-20 Texas Instruments Incorporated Source/drain extension implant process for use with short time anneals
US7150516B2 (en) * 2004-09-28 2006-12-19 Hewlett-Packard Development Company, L.P. Integrated circuit and method for manufacturing
KR100657142B1 (ko) * 2005-06-03 2006-12-13 매그나칩 반도체 유한회사 이미지센서의 픽셀 쉬링크를 위한 콘택 구조 및 그 제조방법
JP6268055B2 (ja) * 2014-07-15 2018-01-24 矢崎総業株式会社 端子及びコネクタ
WO2016010053A1 (ja) * 2014-07-14 2016-01-21 矢崎総業株式会社 電気素子
JP6272744B2 (ja) * 2014-10-24 2018-01-31 矢崎総業株式会社 板状導電体及び板状導電体の表面処理方法
JP6268070B2 (ja) * 2014-09-16 2018-01-24 矢崎総業株式会社 メッキ材及び端子金具
JP6374718B2 (ja) * 2014-07-14 2018-08-15 矢崎総業株式会社 電気素子
US10038081B1 (en) 2017-09-06 2018-07-31 Nxp Usa, Inc. Substrate contacts for a transistor
US10679987B2 (en) * 2017-10-31 2020-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Bootstrap metal-oxide-semiconductor (MOS) device integrated with a high voltage MOS (HVMOS) device and a high voltage junction termination (HVJT) device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4843034A (en) * 1987-06-12 1989-06-27 Massachusetts Institute Of Technology Fabrication of interlayer conductive paths in integrated circuits
CA1276314C (en) * 1988-03-24 1990-11-13 Alexander Kalnitsky Silicon ion implanted semiconductor device
JPH03101255A (ja) * 1989-09-14 1991-04-26 Sony Corp 半導体装置
JPH04162519A (ja) * 1990-10-24 1992-06-08 Sony Corp Ｍｏｓ型半導体装置の製造方法
US5783469A (en) * 1996-12-10 1998-07-21 Advanced Micro Devices, Inc. Method for making nitrogenated gate structure for improved transistor performance
US6017829A (en) * 1997-04-01 2000-01-25 Micron Technology, Inc. Implanted conductor and methods of making
US6074904A (en) * 1998-04-21 2000-06-13 Advanced Micro Devices, Inc. Method and structure for isolating semiconductor devices after transistor formation
US6027961A (en) * 1998-06-30 2000-02-22 Motorola, Inc. CMOS semiconductor devices and method of formation
US6077748A (en) * 1998-10-19 2000-06-20 Advanced Micro Devices, Inc. Advanced trench isolation fabrication scheme for precision polysilicon gate control
KR100281908B1 (ko) * 1998-11-20 2001-02-15 김덕중 반도체소자 및 그 제조방법
JP3723410B2 (ja) * 2000-04-13 2005-12-07 三洋電機株式会社 半導体装置とその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100825466B1 (ko) * 2004-08-06 2008-04-28 오스트리아마이크로시스템즈 아게 고전압 ｎｍｏｓ 트랜지스터 및 그것의 제조 방법

Also Published As

Publication number Publication date
WO2003036702A3 (en) 2003-11-06
WO2003036702A2 (en) 2003-05-01
CN1326210C (zh) 2007-07-11
EP1479101A2 (en) 2004-11-24
JP2006500759A (ja) 2006-01-05
AU2002327714A1 (en) 2003-05-06
CN1592951A (zh) 2005-03-09
US6555915B1 (en) 2003-04-29
US20030075806A1 (en) 2003-04-24

Similar Documents

Publication Publication Date Title
EP0798785B1 (en) High-voltage-resistant MOS transistor, and corresponding manufacturing process
JP3324702B2 (ja) Ｍｏｓトランジスタにおいてセルフアラインソース／ドレインコンタクトを形成する方法
US4661202A (en) Method of manufacturing semiconductor device
US7053465B2 (en) Semiconductor varactor with reduced parasitic resistance
JPH10294430A (ja) Ｓｏｉ集積回路のｅｓｄ保護用の双安定擬似ｓｃｒスイッチ
KR20010033347A (ko) 벌크 씨모스 구조와 양립 가능한 에스오아이 구조
EP1082757B1 (en) Semiconductor device with transparent link area for silicide applications and fabrication thereof
KR20040048985A (ko) 기판에 상호접속을 갖는 집적회로 및 이를 위한 방법
US6274914B1 (en) CMOS integrated circuits including source/drain plug
US7545007B2 (en) MOS varactor with segmented gate doping
JP2006500759A5 (enExample)
US6476452B2 (en) Bipolar/BiCMOS semiconductor device
KR100285002B1 (ko) 반도체장치및그제조방법
US8294218B2 (en) Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection
US8598659B2 (en) Single finger gate transistor
KR100294775B1 (ko) 반도체장치및그의제조방법
KR950001955B1 (ko) 반도체장치와 그 제조방법
KR100349376B1 (ko) 트렌치 측벽을 채널층으로 사용하는 트렌치 트랜지스터의제조 방법
KR100587045B1 (ko) 반도체 소자의 제조 방법
KR100239421B1 (ko) 반도체 소자의 제조 방법
KR0131741B1 (ko) 반도체 기억장치 및 그 제조방법
KR20010086499A (ko) 쏘이 기판을 사용하는 반도체 장치의 형성 방법
KR20050108200A (ko) 바이폴라 정션 트랜지스터의 제조방법
KR19990044743A (ko) 반도체 집적 회로 장치
KR20000045475A (ko) 웰 바이어싱 트랜지스터 형성방법

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20040422

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
N231 Notification of change of applicant
PN2301 Change of applicant

Patent event date: 20041015

Comment text: Notification of Change of Applicant

Patent event code: PN23011R01D

A201 Request for examination
AMND Amendment
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20070927

Comment text: Request for Examination of Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20080731

Patent event code: PE09021S01D

AMND Amendment
E90F Notification of reason for final refusal
PE0902 Notice of grounds for rejection

Comment text: Final Notice of Reason for Refusal

Patent event date: 20081114

Patent event code: PE09021S02D

AMND Amendment
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20090323

Patent event code: PE09021S01D

AMND Amendment
E601 Decision to refuse application
PE0601 Decision on rejection of patent

Patent event date: 20090713

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 20090323

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I

Patent event date: 20081114

Comment text: Final Notice of Reason for Refusal

Patent event code: PE06011S02I

Patent event date: 20080731

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I

J201 Request for trial against refusal decision
PJ0201 Trial against decision of rejection

Patent event date: 20090812

Comment text: Request for Trial against Decision on Refusal

Patent event code: PJ02012R01D

Patent event date: 20090713

Comment text: Decision to Refuse Application

Patent event code: PJ02011S01I

Appeal kind category: Appeal against decision to decline refusal

Decision date: 20101029

Appeal identifier: 2009101007487

Request date: 20090812

AMND Amendment
PB0901 Examination by re-examination before a trial

Comment text: Amendment to Specification, etc.

Patent event date: 20090911

Patent event code: PB09011R02I

Comment text: Request for Trial against Decision on Refusal

Patent event date: 20090812

Patent event code: PB09011R01I

Comment text: Amendment to Specification, etc.

Patent event date: 20090525

Patent event code: PB09011R02I

Comment text: Amendment to Specification, etc.

Patent event date: 20090114

Patent event code: PB09011R02I

Comment text: Amendment to Specification, etc.

Patent event date: 20080930

Patent event code: PB09011R02I

Comment text: Amendment to Specification, etc.

Patent event date: 20070927

Patent event code: PB09011R02I

B601 Maintenance of original decision after re-examination before a trial
PB0601 Maintenance of original decision after re-examination before a trial

Comment text: Report of Result of Re-examination before a Trial

Patent event code: PB06011S01D

Patent event date: 20091006

J301 Trial decision

Free format text: TRIAL DECISION FOR APPEAL AGAINST DECISION TO DECLINE REFUSAL REQUESTED 20090812

Effective date: 20101029

Free format text: TRIAL NUMBER: 2009101007487; TRIAL DECISION FOR APPEAL AGAINST DECISION TO DECLINE REFUSAL REQUESTED 20090812

Effective date: 20101029

PJ1301 Trial decision

Patent event code: PJ13011S01D

Patent event date: 20101029

Comment text: Trial Decision on Objection to Decision on Refusal

Appeal kind category: Appeal against decision to decline refusal

Request date: 20090812

Decision date: 20101029

Appeal identifier: 2009101007487