KR20010066902A - 반도체 장치 - Google Patents
반도체 장치 Download PDFInfo
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- KR20010066902A KR20010066902A KR1020000038202A KR20000038202A KR20010066902A KR 20010066902 A KR20010066902 A KR 20010066902A KR 1020000038202 A KR1020000038202 A KR 1020000038202A KR 20000038202 A KR20000038202 A KR 20000038202A KR 20010066902 A KR20010066902 A KR 20010066902A
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Abstract
Description
Claims (6)
- 반도체 회로의 베어칩을 복수단 적층하며, 상하의 외부 전극끼리를 접속한 반도체 장치에 있어서,상기 베어칩의 외부전극으로서, 베어칩을 선택하기 위한 소정의 배열 피치로서 배열된 복수의 칩 셀렉트 전극과, 베어칩을 기능시키는 신호가 공급되는 복수의 신호전극을 포함하며,각 베어칩이 상기 칩 셀렉트 전극의 배열피치와 동일 거리만큼 그 배열방향으로 벗어나서 적층되며, 상기 각 신호전극에 대향하는 베어칩의 대응전극과의 접속점이 상기 칩 셀렉트 전극의 배열방향으로 상기 배열 칩 분 만큼 벗어나 있는 것을 특징으로 하는 반도체 장치.
- 제 1항에 있어서, 상기 외부전극은 상기 베어칩을 적층하는 방향의 표면(surface)과 속면(back)에 형성되며, 상기 표면과 속면의 각 전극끼리가 상호 접속되어 있는 것을 특징으로 하는 반도체 장치.
- 제 1항 또는 제 2항에 있어서, 상기 베어칩은 상기 복수의 칩 셀렉트 전극중, 상기 베어칩의 한 변에 가장 가까운 측의 제 1칩 셀렉트 전극으로부터의 칩 셀렉트 신호를 검출하며, 그 밖의 칩 셀렉트 전극은 다른 베어칩의 칩 셀렉트 전극에 접속되는 것을 특징으로 하는 반도체 장치.
- 제 1항 또는 제 2항에 있어서, 상기 베어칩의 각 단의 외부전극은 접속 범프를 통해 접속되어 있는 것을 특징으로 하는 반도체 장치.
- 제 1항 또는 제 2항에 있어서, 상기 표면과 속면의 각 전극끼리가 상기 베어칩 내에서 전기적으로 접속되어 있는 것을 특징으로 하는 반도체 장치.
- 제 1항 또는 제 2항에 있어서, 상기 표면과 속면의 각 전극끼리가 상기 베어칩 내 및 베어칩 표면의 배선에 의해 전기적으로 접속되어 있는 것을 특징으로 하는 반도체 장치.
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JP19396299A JP3356122B2 (ja) | 1999-07-08 | 1999-07-08 | システム半導体装置及びシステム半導体装置の製造方法 |
JP???11-193963 | 1999-07-08 | ||
JP??11?????1939 | 1999-07-08 |
Publications (2)
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KR20010066902A true KR20010066902A (ko) | 2001-07-11 |
KR100340116B1 KR100340116B1 (ko) | 2002-06-10 |
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KR1020000038202A KR100340116B1 (ko) | 1999-07-08 | 2000-07-05 | 반도체 장치 |
KR1020000038525A KR20010066906A (ko) | 1999-07-08 | 2000-07-06 | 시스템 반도체 장치 및 그 제조 방법 |
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KR1020000038525A KR20010066906A (ko) | 1999-07-08 | 2000-07-06 | 시스템 반도체 장치 및 그 제조 방법 |
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US (2) | US7098538B1 (ko) |
JP (1) | JP3356122B2 (ko) |
KR (2) | KR100340116B1 (ko) |
TW (1) | TW466741B (ko) |
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US7768114B2 (en) | 2008-06-30 | 2010-08-03 | Hynix Semiconductor Inc. | Semiconductor package, stacked semiconductor package having the same, and a method for selecting one semiconductor chip in a stacked semiconductor package |
KR101009502B1 (ko) * | 2007-07-17 | 2011-01-18 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 장치 |
US8218346B2 (en) | 2009-03-20 | 2012-07-10 | Samsung Electronics Co., Ltd. | Multi-chip packages including extra memory chips to define additional logical packages and related devices |
US8729686B2 (en) | 2010-12-07 | 2014-05-20 | SK Hynix Inc. | Semiconductor package and a method for selecting a chip in the semiconductor package |
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JP4982932B2 (ja) * | 2001-09-03 | 2012-07-25 | ソニー株式会社 | 画像表示装置の製造方法 |
KR20030060268A (ko) * | 2002-01-08 | 2003-07-16 | 주식회사 심텍 | 본딩패드 접속용 비아홀을 이용한 비지에이 반도체패키지의 제조방법 및 그 구조 |
WO2004051729A2 (de) * | 2002-12-04 | 2004-06-17 | Süss Mircro Tec Lithography Gmbh | Verfahren und vorrichtung zur vorbehandlung der oberflächen von zu bondenden substraten |
JP4039998B2 (ja) * | 2003-09-03 | 2008-01-30 | 沖電気工業株式会社 | 半導体装置及び半導体集積回路装置 |
US7327006B2 (en) * | 2005-06-23 | 2008-02-05 | Nokia Corporation | Semiconductor package |
US7473577B2 (en) * | 2006-08-11 | 2009-01-06 | International Business Machines Corporation | Integrated chip carrier with compliant interconnect |
JP2008294423A (ja) | 2007-04-24 | 2008-12-04 | Nec Electronics Corp | 半導体装置 |
US20100148218A1 (en) * | 2008-12-10 | 2010-06-17 | Panasonic Corporation | Semiconductor integrated circuit device and method for designing the same |
FR2946795B1 (fr) * | 2009-06-12 | 2011-07-22 | 3D Plus | Procede de positionnement des puces lors de la fabrication d'une plaque reconstituee |
JP5340047B2 (ja) | 2009-06-12 | 2013-11-13 | パナソニック株式会社 | 半導体集積回路装置 |
WO2013059757A1 (en) * | 2011-10-21 | 2013-04-25 | Santa Barbara Infrared, Inc. | Techniques for tiling arrays of pixel elements |
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2000
- 2000-07-05 KR KR1020000038202A patent/KR100340116B1/ko active IP Right Grant
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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KR101009502B1 (ko) * | 2007-07-17 | 2011-01-18 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 장치 |
US7768114B2 (en) | 2008-06-30 | 2010-08-03 | Hynix Semiconductor Inc. | Semiconductor package, stacked semiconductor package having the same, and a method for selecting one semiconductor chip in a stacked semiconductor package |
US8168450B2 (en) | 2008-06-30 | 2012-05-01 | Hynix Semiconductor Inc. | Semiconductor package, stacked semiconductor package having the same, and a method for selecting one semiconductor chip in a stacked semiconductor package |
US8218346B2 (en) | 2009-03-20 | 2012-07-10 | Samsung Electronics Co., Ltd. | Multi-chip packages including extra memory chips to define additional logical packages and related devices |
US8729686B2 (en) | 2010-12-07 | 2014-05-20 | SK Hynix Inc. | Semiconductor package and a method for selecting a chip in the semiconductor package |
Also Published As
Publication number | Publication date |
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US7098538B1 (en) | 2006-08-29 |
KR20010066906A (ko) | 2001-07-11 |
US7297575B2 (en) | 2007-11-20 |
JP2001024089A (ja) | 2001-01-26 |
JP3356122B2 (ja) | 2002-12-09 |
KR100340116B1 (ko) | 2002-06-10 |
US20050179057A1 (en) | 2005-08-18 |
TW466741B (en) | 2001-12-01 |
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