KR20010020781A - 반도체 집적 회로 장치의 제조 방법 - Google Patents

반도체 집적 회로 장치의 제조 방법 Download PDF

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Publication number
KR20010020781A
KR20010020781A KR1020000022126A KR20000022126A KR20010020781A KR 20010020781 A KR20010020781 A KR 20010020781A KR 1020000022126 A KR1020000022126 A KR 1020000022126A KR 20000022126 A KR20000022126 A KR 20000022126A KR 20010020781 A KR20010020781 A KR 20010020781A
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KR
South Korea
Prior art keywords
insulating film
film
forming
semiconductor substrate
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020000022126A
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English (en)
Korean (ko)
Inventor
간다다까유끼
히라이와아쯔시
스즈끼노리오
사까이사또시
이께다슈우지
요시다야스꼬
호리베신이찌
Original Assignee
가나이 쓰토무
가부시키가이샤 히타치세이사쿠쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가나이 쓰토무, 가부시키가이샤 히타치세이사쿠쇼 filed Critical 가나이 쓰토무
Publication of KR20010020781A publication Critical patent/KR20010020781A/ko
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181Manufacturing their gate insulating layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188Manufacturing their isolation regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1020000022126A 1999-04-26 2000-04-26 반도체 집적 회로 장치의 제조 방법 Withdrawn KR20010020781A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP11781599 1999-04-26
JP1999-117815 1999-04-26
JP1999-225991 1999-08-10
JP22599199A JP4149095B2 (ja) 1999-04-26 1999-08-10 半導体集積回路装置の製造方法

Publications (1)

Publication Number Publication Date
KR20010020781A true KR20010020781A (ko) 2001-03-15

Family

ID=26455865

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000022126A Withdrawn KR20010020781A (ko) 1999-04-26 2000-04-26 반도체 집적 회로 장치의 제조 방법

Country Status (3)

Country Link
US (2) US6713353B1 (https=)
JP (1) JP4149095B2 (https=)
KR (1) KR20010020781A (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4951585B2 (ja) * 1999-04-26 2012-06-13 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
US6503851B2 (en) * 2000-08-31 2003-01-07 Micron Technology, Inc. Use of linear injectors to deposit uniform selective ozone TEOS oxide film by pulsing reactants on and off
US6368986B1 (en) * 2000-08-31 2002-04-09 Micron Technology, Inc. Use of selective ozone TEOS oxide to create variable thickness layers and spacers
JP3746968B2 (ja) * 2001-08-29 2006-02-22 東京エレクトロン株式会社 絶縁膜の形成方法および形成システム
JP2003152102A (ja) 2001-11-15 2003-05-23 Hitachi Ltd 半導体集積回路装置の製造方法
JPWO2003049188A1 (ja) 2001-11-30 2005-04-21 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
KR100466208B1 (ko) * 2002-07-08 2005-01-13 매그나칩 반도체 유한회사 반도체 소자의 제조 방법
JP2004087960A (ja) * 2002-08-28 2004-03-18 Fujitsu Ltd 半導体装置の製造方法
JP2004095886A (ja) * 2002-08-30 2004-03-25 Fujitsu Ltd 半導体装置及びその製造方法
KR100874647B1 (ko) * 2002-09-17 2008-12-17 엘지디스플레이 주식회사 액정표시소자 및 그 제조 방법
GB2394231A (en) * 2002-10-17 2004-04-21 Lohmann Gmbh & Co Kg Non-woven textile structure incorporating stabilized filament assemblies
US6706581B1 (en) * 2002-10-29 2004-03-16 Taiwan Semiconductor Manufacturing Company Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices
JP2004363214A (ja) * 2003-06-03 2004-12-24 Renesas Technology Corp 半導体集積回路装置の製造方法および半導体集積回路装置
US7132350B2 (en) * 2003-07-21 2006-11-07 Macronix International Co., Ltd. Method for manufacturing a programmable eraseless memory
JP5015420B2 (ja) * 2003-08-15 2012-08-29 旺宏電子股▲ふん▼有限公司 プログラマブル消去不要メモリに対するプログラミング方法
KR100541817B1 (ko) * 2003-10-14 2006-01-11 삼성전자주식회사 듀얼 게이트 절연막 형성 방법
US7084035B2 (en) 2004-04-13 2006-08-01 Ricoh Company, Ltd. Semiconductor device placing high, medium, and low voltage transistors on the same substrate
JP2005353892A (ja) * 2004-06-11 2005-12-22 Seiko Epson Corp 半導体基板、半導体装置及びその製造方法
WO2006092846A1 (ja) * 2005-03-01 2006-09-08 Fujitsu Limited 半導体装置及びその製造方法
US7011980B1 (en) 2005-05-09 2006-03-14 International Business Machines Corporation Method and structures for measuring gate tunneling leakage parameters of field effect transistors
KR100719219B1 (ko) * 2005-09-20 2007-05-16 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
US7968148B2 (en) * 2006-09-15 2011-06-28 Globalfoundries Singapore Pte. Ltd. Integrated circuit system with clean surfaces
JP2008270837A (ja) * 2008-06-26 2008-11-06 Renesas Technology Corp 半導体集積回路装置
KR101092317B1 (ko) * 2009-04-10 2011-12-09 주식회사 하이닉스반도체 반도체 소자의 제조방법
JP5278132B2 (ja) * 2009-04-16 2013-09-04 富士通セミコンダクター株式会社 半導体装置の製造方法
CN102646595A (zh) * 2011-11-11 2012-08-22 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、显示器件
US9373501B2 (en) * 2013-04-16 2016-06-21 International Business Machines Corporation Hydroxyl group termination for nucleation of a dielectric metallic oxide
JP7101090B2 (ja) 2018-09-12 2022-07-14 株式会社東芝 半導体装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0681319B1 (en) * 1994-04-15 2002-10-30 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
TW312831B (en) * 1996-08-16 1997-08-11 United Microelectronics Corp Manufacturing method of semiconductor memory device with capacitor(3)

Also Published As

Publication number Publication date
US6821854B2 (en) 2004-11-23
JP4149095B2 (ja) 2008-09-10
JP2001015612A (ja) 2001-01-19
US6713353B1 (en) 2004-03-30
US20030003639A1 (en) 2003-01-02

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20000426

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid