KR102200850B1 - 지지 유리 기판 및 이것을 사용한 반송체 - Google Patents

지지 유리 기판 및 이것을 사용한 반송체 Download PDF

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Publication number
KR102200850B1
KR102200850B1 KR1020157032898A KR20157032898A KR102200850B1 KR 102200850 B1 KR102200850 B1 KR 102200850B1 KR 1020157032898 A KR1020157032898 A KR 1020157032898A KR 20157032898 A KR20157032898 A KR 20157032898A KR 102200850 B1 KR102200850 B1 KR 102200850B1
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South Korea
Prior art keywords
glass substrate
substrate
carrier
less
supporting glass
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KR1020157032898A
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English (en)
Korean (ko)
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KR20160055104A (ko
Inventor
신키치 미와
히카루 이케다
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니폰 덴키 가라스 가부시키가이샤
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Publication of KR20160055104A publication Critical patent/KR20160055104A/ko
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    • CCHEMISTRY; METALLURGY
    • C03GLASS; MINERAL OR SLAG WOOL
    • C03CCHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C3/00Glass compositions
    • C03C3/04Glass compositions containing silica
    • C03C3/076Glass compositions containing silica with 40% to 90% silica, by weight
    • C03C3/089Glass compositions containing silica with 40% to 90% silica, by weight containing boron
    • C03C3/091Glass compositions containing silica with 40% to 90% silica, by weight containing boron containing aluminium
    • C03C3/093Glass compositions containing silica with 40% to 90% silica, by weight containing boron containing aluminium containing zinc or zirconium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02422Non-crystalline insulating materials, e.g. glass, polymers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67715Changing the direction of the conveying path
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68757Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15Ceramic or glass substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Materials Engineering (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Organic Chemistry (AREA)
  • Geochemistry & Mineralogy (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Glass Compositions (AREA)
  • Ceramic Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
KR1020157032898A 2013-09-12 2014-09-02 지지 유리 기판 및 이것을 사용한 반송체 KR102200850B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JPJP-P-2013-189065 2013-09-12
JP2013189065 2013-09-12
PCT/JP2014/073085 WO2015037478A1 (ja) 2013-09-12 2014-09-02 支持ガラス基板及びこれを用いた搬送体

Publications (2)

Publication Number Publication Date
KR20160055104A KR20160055104A (ko) 2016-05-17
KR102200850B1 true KR102200850B1 (ko) 2021-01-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020157032898A KR102200850B1 (ko) 2013-09-12 2014-09-02 지지 유리 기판 및 이것을 사용한 반송체

Country Status (5)

Country Link
JP (1) JP6593669B2 (zh)
KR (1) KR102200850B1 (zh)
CN (2) CN112159100A (zh)
TW (1) TWI644881B (zh)
WO (1) WO2015037478A1 (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6119567B2 (ja) * 2013-11-11 2017-04-26 旭硝子株式会社 ガラス積層体の製造方法および電子デバイスの製造方法
CN115636583A (zh) * 2014-04-07 2023-01-24 日本电气硝子株式会社 支承玻璃基板及使用其的层叠体
CN115108719A (zh) * 2014-09-03 2022-09-27 日本电气硝子株式会社 支承玻璃基板及使用其的层叠体
JP6631935B2 (ja) * 2015-01-05 2020-01-15 日本電気硝子株式会社 ガラス板の製造方法
JP6742593B2 (ja) * 2015-01-05 2020-08-19 日本電気硝子株式会社 支持ガラス基板の製造方法及び積層体の製造方法
WO2016143583A1 (ja) * 2015-03-10 2016-09-15 日本電気硝子株式会社 半導体用支持ガラス基板及びこれを用いた積層基板
KR102515348B1 (ko) 2015-05-28 2023-03-30 에이지씨 가부시키가이샤 유리 기판 및 적층 기판
TWI631688B (zh) * 2015-06-16 2018-08-01 勤友光電股份有限公司 用於雷射剝離處理之晶圓結構
KR20180033193A (ko) * 2015-07-24 2018-04-02 아사히 가라스 가부시키가이샤 유리 기판, 적층 기판, 적층 기판의 제조 방법, 적층체, 곤포체, 및 유리 기판의 제조 방법
CN117865461A (zh) * 2015-10-02 2024-04-12 Agc株式会社 玻璃基板、层叠基板和层叠体
WO2017104514A1 (ja) * 2015-12-16 2017-06-22 日本電気硝子株式会社 支持結晶化ガラス基板及びこれを用いた積層体
WO2017104513A1 (ja) * 2015-12-17 2017-06-22 日本電気硝子株式会社 支持ガラス基板の製造方法
JP6819613B2 (ja) 2015-12-28 2021-01-27 Agc株式会社 ガラス基板、積層基板、積層体、および半導体パッケージの製造方法
WO2018051987A1 (ja) 2016-09-16 2018-03-22 旭硝子株式会社 ガラス基板、および積層基板
DE102018209589B4 (de) * 2017-06-22 2023-05-04 Schott Ag Verbund aus einem Bauteil, insbesondere einem elektronischen Bauteil, und einem Glas- oder Glaskeramikmaterial sowie Verfahren zu dessen Herstellung

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009164314A (ja) * 2007-12-30 2009-07-23 Fujikura Ltd 貼り合わせ基板および貼り合せ基板を用いた半導体装置の製造方法
JP2011136895A (ja) * 2009-12-04 2011-07-14 Nippon Electric Glass Co Ltd 合わせガラス

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JPH0230640A (ja) * 1988-07-19 1990-02-01 Nippon Electric Glass Co Ltd ファイバープレート用芯ガラス
JPH03237036A (ja) * 1989-08-24 1991-10-22 Nippon Electric Glass Co Ltd アルミナパッケージ用薄板状硼けい酸ガラス
JP5378158B2 (ja) * 2003-02-19 2013-12-25 日本電気硝子株式会社 半導体パッケージ用カバーガラス
JP4716245B2 (ja) * 2004-11-11 2011-07-06 日本電気硝子株式会社 ガラス基板及びその製造方法
JP5348598B2 (ja) * 2005-05-10 2013-11-20 日本電気硝子株式会社 半導体素子用ガラス基板およびそれを用いたチップスケールパッケージ
JP2007311492A (ja) * 2006-05-17 2007-11-29 Shinko Electric Ind Co Ltd 半導体装置の製造方法
US20080191334A1 (en) * 2007-02-12 2008-08-14 Visera Technologies Company Limited Glass dam structures for imaging devices chip scale package
JP2009016771A (ja) * 2007-06-08 2009-01-22 Hoya Candeo Optronics株式会社 ウエハ支持ガラス
JP5091696B2 (ja) * 2008-01-26 2012-12-05 株式会社フジクラ 半導体パッケージの製造方法
JP5496692B2 (ja) * 2010-01-22 2014-05-21 三洋電機株式会社 半導体モジュールの製造方法
JP5573422B2 (ja) * 2010-06-29 2014-08-20 富士通株式会社 半導体装置の製造方法
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Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
JP2009164314A (ja) * 2007-12-30 2009-07-23 Fujikura Ltd 貼り合わせ基板および貼り合せ基板を用いた半導体装置の製造方法
JP2011136895A (ja) * 2009-12-04 2011-07-14 Nippon Electric Glass Co Ltd 合わせガラス

Also Published As

Publication number Publication date
TW201522269A (zh) 2015-06-16
JP6593669B2 (ja) 2019-10-23
JP2015078113A (ja) 2015-04-23
CN112159100A (zh) 2021-01-01
WO2015037478A1 (ja) 2015-03-19
CN105307993A (zh) 2016-02-03
TWI644881B (zh) 2018-12-21
KR20160055104A (ko) 2016-05-17

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