KR102044045B1 - 상이한 소수 캐리어 수명들을 가진 채널 영역을 포함한 장치들 및 방법들 - Google Patents

상이한 소수 캐리어 수명들을 가진 채널 영역을 포함한 장치들 및 방법들 Download PDF

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KR102044045B1
KR102044045B1 KR1020147006540A KR20147006540A KR102044045B1 KR 102044045 B1 KR102044045 B1 KR 102044045B1 KR 1020147006540 A KR1020147006540 A KR 1020147006540A KR 20147006540 A KR20147006540 A KR 20147006540A KR 102044045 B1 KR102044045 B1 KR 102044045B1
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forming
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elongated channel
channel region
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KR20140068061A (ko
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파올로 태사리올
아우렐리오 지안까를로 마우리
아끼라 고다
이지에 자오
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마이크론 테크놀로지, 인크.
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions

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  • Semiconductor Memories (AREA)
KR1020147006540A 2011-08-16 2012-08-14 상이한 소수 캐리어 수명들을 가진 채널 영역을 포함한 장치들 및 방법들 Active KR102044045B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/211,033 US8742481B2 (en) 2011-08-16 2011-08-16 Apparatuses and methods comprising a channel region having different minority carrier lifetimes
US13/211,033 2011-08-16
PCT/US2012/050796 WO2013025719A2 (en) 2011-08-16 2012-08-14 Apparatuses and methods comprising a channel region having different minority carrier lifetimes

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KR20140068061A KR20140068061A (ko) 2014-06-05
KR102044045B1 true KR102044045B1 (ko) 2019-12-02

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Country Link
US (2) US8742481B2 (enExample)
EP (1) EP2745321A4 (enExample)
JP (1) JP5877246B2 (enExample)
KR (1) KR102044045B1 (enExample)
CN (1) CN103828049A (enExample)
TW (1) TWI538165B (enExample)
WO (1) WO2013025719A2 (enExample)

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US20130043505A1 (en) 2013-02-21
US9190472B2 (en) 2015-11-17
TW201316489A (zh) 2013-04-16
WO2013025719A2 (en) 2013-02-21
US8742481B2 (en) 2014-06-03
WO2013025719A3 (en) 2013-05-02
EP2745321A4 (en) 2015-04-01
KR20140068061A (ko) 2014-06-05
TWI538165B (zh) 2016-06-11
EP2745321A2 (en) 2014-06-25
JP2014522131A (ja) 2014-08-28
CN103828049A (zh) 2014-05-28
US20140264447A1 (en) 2014-09-18
JP5877246B2 (ja) 2016-03-02

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