Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
  • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
  • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
  • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
  • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions

Definitions

• Forming memory devices laterally on a surface of a semiconductor chip uses a great deal of chip real estate. Improved memory devices are needed with new configurations to further increase memory density beyond traditional memory devices.
• FIG. 1A shows a memory device according to an embodiment of the invention.
• FIG. IB shows a block diagram of a memory string from Figure
• FIG. 1C shows a model of carrier generation in operation of a memory siring according to an embodiment of the invention
• FIG. ID shows a model of carrier generation in operation of a memory string according to an embodiment of the invention.
• FIG. 2 shows a graph of potential versus time for channel region of a memory siring according to an embodiment of the invention.
• FIG. 3A shows another memory device according to an embodiment of the inv ention.
• FIG. 3B shows another memory device according to an embodiment of the invention.
• FIG. 4A-4I show processing operations for a memory device according to an embodiment of the invention.
• FIG. 5 shows an information handling system using a memory device according to an embodiment of the invention.
• Figure 1A shows an apparatus in the form of a memory device 100 formed on a substrate 102.
• Figure IB shows a memory siring 101 from Figure 1A.
• Charge storage structures 1 12 e.g., a combination of a tunnel dielectric, polysilicon, and a charge blocking material; a combination of a nitride, an oxide, and a nitride; or any other combination of materials that can provide a charge storage function, whether currently known or developed in the future, substantially surround an elongated channel region 1 10, as shown in
• FIG. IB to form a respective charge storage structure corresponding to each of a plurality of memory cell gates 1 14 (which may also substantially surround respective cross sections of the elongated channel region 110 and charge storage structure(s) 1 12).
• the charge storage structures may be a respective plurality of portions of a single structure, or may comprises a plurality of separate, discrete structures.
• a first select gate 120 and a second select gate 122 are shown to selectively couple the elongated channel region 110 to source region 130 and a drain region 132, respectively.
• a dielectric 104 can fill in spaces between components such as those described above.
• the elongated channel region 110 is formed from a semiconductor material, such as p-type and/or undoped polysilicon.
• the elongated channel region 1 10 can be formed in multiple process actions, such as where a first end 1 1 1 is formed in a different polysilicon deposition activity than that used to form other portions of the elongated channel region 110, such as the second end 1 13 and/or a middle portion,
• a source region 130 and a drain region 132 are shown coupled to the first end 11 1 and the second end 1 13 of the elongated channel region 1 10, respectively.
• the source region 130 and the drain region include n-type semiconductor material, such as n+ polysilicon.
• the path comprising source region 130, elongated channel region 1 10, and drain region 132 acts as an n-p-n transistor, with select gates 120, 122, and memory cell gates 114 operating to allow (or inhibit) signal transmission along the way.
• Components comprising the source region 130, the elongated channel region 1 10, the drain region 132, select gates 120, 122, charge storage structures 1 12, and memory cell gates 114 together form a memory string 101.
• the memory string is configured in a circuit to operate as a NA D memor string.
• a source line 126 and a data line, such as bitline 128, are shown coupled to the source region 130 and the drain region 132, respectively.
• the source line 126 and bitline 128 can comprise, consist of, or consist essentially of metal, such as aluminum, copper, or tungsten, or alloys of these or other conductor metals.
• metal further comprises metal nitrides, or other materials that, operate primarily as conductors.
• Figure IB shows a block diagram of memory string 101 from
• FIG. 1 A The number of memory cell gates 1 14 shown in the figures are for illustration purposes only.
• memory string 101 comprises eight memory cell gates 114 between the select gates 120, 122.
• the channel region 1 10 can include a first recombination region
• first recombination region 106 and the second recombination region 108 are formed as part of the elongated channel region 110, and can be of the same conductivity type.
• the first recombination region 106 and the second recombination region 108 are configured to have a minority carrier lifetime that is lower than the minority carrier lifetime of the body region of the elongated channel region 1 10.
• the first recombination region 106 and the second recombination region 108 are formed in substantially similar configurations, and have substantially the same minority carrier lifetime.
• the first recombination region 106 and the second recombination region 108 are formed in substantially similar configurations, and have substantially the same minority carrier lifetime.
• recombination region 108 have different minority carrier lifetimes, where both minority carrier lifetimes are lower than the minority carrier lifetime of the body region of the elongated channel region 1 10.
• first recombination region 106 and the second recombination region 108 are doped to a higher concentration than the body region 110 to provide the lower minority carrier lifetime.
• the elongated channel region (comprising the first and second recombination regions 106, 108) is doped with a p-type dopant. Examples of p- type dopants include, but are not limited to, boron, aluminum, gallium, and indium.
• One example of doping concentrations comprises the body region of the elongated channel region 1 10 being doped to a concentration of approximately 1 x 10 18 atoms/cm 3 , with the first recombination region 106 and the second recombination region 108 being doped to a concentration of approximately 5 x 10 IS atoms/cm' or higher.
• the higher doping concentration in the first recombination region 106 and the second recombination region 108 results in a lower minority carrier lifetime than in the body region of the elongated channel region 110.
• Another example includes the elongated channel region 110 being imdoped, with the first recombination region 106 and the second recombination region 108 being doped to an effective concentration higher than the undoped body region 1 10.
• a lower minority carrier lifetime in regions outside the plurality of memor cell gates 1 14 should provide better selective isolation of the elongated channel region 1 10 during memory operations.
• the string 101 may be selected for erasure. It is desirable in this case for other strings 101 to be isolated.
• Figure lC shows a modeled example of the elongated channel region 1 10, recombination region 108, and memoiy cell gates 114,
• the Figure shows that in the impact ionization regions, carrier generation is sustained by the potential drop during an inhibit condition for unselected strings in an operation such as an era se operation. Without application of embodiments of the present invention, the boosted channel may lose its potential over a short time.
• Figure I D shows channel region potential 154 for a device without recombination regions. As can be seen from the Figure, the channel region potential 154 degrades over time.
• the channel region potential 152 is shown to be maintained over the same time period.
• strain engineering and alternative material choice include strain engineering and alternative material choice.
• an impurity element that may or may not include dopant elements is implanted or otherwise introduced into the lattice within the first recombination region 106 and the second recombination region 108.
• the strain provided to the lattice by the addition of the impurity element(s) modifies the regions (i.e., results in the regions having a different lattice strain condition than the body region), which results in the regions having a lower minority carrier lifetime than the body region of the elongated channel region 1 10.
• the first recombination region 106 and the second recombination region 108 are formed from a different semiconductor material than that used to form the body region of the elongated channel region 1 10.
• the different properties of the material choice results in a lower minority carrier lifetime in the recombination regions 106, 108 than in the body region of the elongated channel region 110.
• Figure ID shows a modeled example of a material engineered example. As can be seen, the channel region potential 150 for a material engineered example is shown to be maintained over time.
• first recombination region 106 and the second recombination region 108 each extend at least from (in the case of region 106) and/or to (in the case of region 108) respective locations within the select gates 122, 120.
• Figure IB shows an example where the first recombination region 106 and the second recombination region 108 each extend from and/or to respective edges of the select gates 122, 120,
• Figure 2 shows a memory string 201.
• the memory string 201 comprises a source region 230 and a drain region 232 with an elongated channel region 210 coupled therebetween.
• a number of memory cell gates 214 are shown adjacent to the elongated channel region 210, separated from the elongated channel region 210 by a number of charge storage structures 212.
• a first select gate 220 is located at a first end 21 1 of the elongated channel region 210, and a second select gate 222 is located at a second end 213 of the elongated channel region 210.
• the elongated channel region 210 comprises a first recombination region 206 and a second recombination region 208 (and an elongated body region between the first and second recombination regions 206, 208).
• the first recombination region 206 and the second recombination region 208 each extend from and/or to respective locations before and/or past edges of the select gates 220, 222.
• the first recombination region 206 extends from a location before an edge of the select gate 220 (e.g., it extends from an edge 216 of the memory cell gates 214) and the second recombination region 208 extends to a location past an edge of the select gates 222 (e.g., it extends to another edge 217 of the memory cell gates 214).
• Figures 1A, IB, and Figure 2 illustrate memory strings that are vertical in orientation. Other configurations are also possible, comprising horizontal and "U” shaped.
• Figures 3A and 3B illustrate examples of "U" shaped memory strings.
• Figure 3A shows a memory string 300, comprising a source region 332 and a drain region 334, with an elongated channel region 310 coupled therebetween and a number of memory cell gates 314 located along a length of the elongated channel region 310.
• the source region 332 and drain region 334 are upward facing, with the elongated channel region 310 forming the "U" shape.
• the elongated channel region 310 comprises a first recombination region 306 and a second recombination region 308 (and a body region therebetween).
• the first recombination region 306 and second recombination region 308 are formed as described above, using heavier doping, strain engineering, or different material choice than what is used to form the body region of the elongated channel region 310,
• Figure 3 A shows the first recombination region 306 and second recombination region 308 each extending from respective edges of a first select gate 320 and a second select gate 322 respectively.
• Figure 3B shows similar memory string 350, with a first recombination region 356 and a second recombination region 358 extending from locations before respective edges of the first select gate 320 and the second select gate 322 (e.g., each extending from an edge 360 of the number of gates 314.
• FIG. 4A-4I describe an example process that can be used to form a vertical memoiy siring. This process can be used as a general guideline to forming the configurations discussed previously, as well as other configurations.
• Figure 4 A shows formation of an n-type doped region 404 on part of a substrate 402.
• a portion of the substrate 402 forms a source line.
• the n-type doped region 404 is heavily doped to be n+.
• a dielectric layer 405 is formed, and a layer of polysilicon 406 is formed.
• the polysilicon 406 is patterned and etched to form openings 408 that isolate portions of the polysilicon 406.
• a first recombination region 410 is formed through portions of the polysilicon 406 that form first select gates 416.
• the first recombination region 410 is deposited as doped polysilicon.
• a material for the first recombination region 410 is deposited and subsequently doped, such as by diffusion, ion implantation, or other doping methods.
• the first recombination region 410 is heavily doped to be p ⁇ .
• the first recombination region 410 comprises a dopant concentration of approximately 5 x 10 1 * atoms/cm 3 .
• the first recombination region 410 is formed by strain engineering.
• strain engineering comprises forming a poiysilicon structure, and implanting or otherwise forming with an impurity element that strains the lattice of the first recombination region 410 to modify a minority carrier lifetime in the first recombination region 410.
• the first recombination region 410 is formed from a material having a lower minority carrier lifetime than a subsequently formed body region 412 of the elongated channel region.
• the material choice for the first recombination region 410 comprises non-silicon semiconductors, such as gallium arsenide, germanium, etc.
• the first recombination region 410 extends from the doped region 404 through the poiysilicon 406, to an edge of the first select gate 416. In other examples, as shown in Figure 2, the first recombination region 410 extends past the edge of the first select gate 416 and up to an edge of a number of memory cell gates. In many embodiments, the first recombination region 410 is a part of an elongated channel region thai is formed in multiple processing operations.
• Figure 4E shows the formation of a body region 412 of the elongated channel region, and formation of a number of memory cell gates 414 along a length of the body region 412 of the elongated channel region.
• the body region 412 is p-type doped, but in other examples it could be doped differently or undoped.
• the region 412 comprises a p- type dopant concentration of approximately 1 x 10 s 8 atoms/cm 3 .
• the body region 412 is a part of an elongated channel region that is formed in multiple processing operations.
• Figure 4F shows formation of another poiysilicon layer 418.
• the poiysilicon layer 418 is patterned and etched to form second select gates 420.
• the first select gate 416 is shared by two adjacent strings 422, while each second select gate 420 is dedicated to an individual memory string 422.
• Other examples include combinations of shared second select gates 420 and individual first select gates 420, depending on the requirements of a memory device configuration.
• a second recombination region 424 is formed through the second select gates 420.
• the second recombination region 424 is deposited as doped polysilicon.
• a material for the second recombination region 424 is deposited and subsequently doped, such as by diffusion, ion implantation, or other doping methods.
• the second recombination region 424 is heavily doped to be p+.
• the second recombination region 424 comprises a dopant concentration of approximately 5 x 10 18 atoms/cm 3 .
• Other examples such as strain engineering, or material choice as is the case with the first recombination region 410, can be used in the second recombination region 424 to provide a lower minority carrier lifetime than the body region 412 of the elongated channel region.
• the second recombination region 424 extends from an edge of the second select gates 420. In other examples, as shown in Figure 2, the second recombination region 424 extends from an edge of the number of memory cell gates 414. As noted above, the second recombination region 424 is a part of an elongated channel region that is formed in multiple processing operations.
• an n-type doped region 426 is formed such that it is connected to the second recombination region 424.
• the n-type doped region 426, the elongated channel region (comprising the second recombination region 424, the body region 412, and the first recombination region 410) and the n-type doped region 404 form an n-p-n junction that functions as a memory string.
• a data line 428 (e.g. a bit line) is formed to connect memory strings and form a memory device.
• FIG. 5 is a block diagram of an information handling system 500 incorporating one or more memory devices 507 according to embodiments of the in vention as described above.
• Information handling system 500 is merely one embodiment of an electronic system in which memory devices of the present invention can be used.
• Other examples include, but are not limited to, tablet computers, cameras, personal data assistants (PDAs), cellular telephones, MP3 players, aircraft, satellites, military vehicles, etc.
• information handling system 500 comprises a data, processing system that comprises a system bus 502 to couple the various components of the system.
• System bus 502 provides communications links among the various components of the information handling system 500 and may be implemented as a single bus, as a combination of busses, or in any other suitable manner,
• Chip assembly 504 is coupled to the system bus 502.
• Chip assembly 504 may include any circuit or operably compatible combination of circuits.
• chip assembly 504 comprises a processor 506 that can be of any type.
• processor means any type of
• computational circuit such as, but not limited to, a microprocessor, a
• microcontroller a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit.
• DSP digital signal processor
• a memory device 507 is included in the chip assembly 504.
• the memory device 507 comprises a memory- device, such as a NAND memory device according to embodiments described above.
• the memory device 507 formed according to the processes described herein may also be embodied as a separate device or chip (not forming part of the chip assembly 504, in combination wit a processor 506 and/or logic 508) coupled to the bus 502.
• additional logic chips 508 other than processor chips are included in the chip assembly 504.
• An example of a logic chip 508 other than a processor comprises an analog to digital converter.
• Other circuits on logic chips 508 such as custom circuits, an application-specific integrated circuit (ASIC), etc. are also included in one embodiment of the invention.
• Information handling system 500 may also include an external memory 511, which in turn can include one or more memory elements suitable to the particular application, such as one or more hard drives 512, and/or one or more drives that handle removable media 513 such as compact disks (CDs), flash drives, digital video disks (DVDs), and the like.
• an external memory 511 which in turn can include one or more memory elements suitable to the particular application, such as one or more hard drives 512, and/or one or more drives that handle removable media 513 such as compact disks (CDs), flash drives, digital video disks (DVDs), and the like.
• CDs compact disks
• DVDs digital video disks
• a semiconductor memory die constructed as described in examples above is included in the information handling system 500, perhaps as part of the memory 511.
• Information handling system 500 may also include a display device 509 such as a monitor or touch screen, additional peripheral components 510, such as speakers, etc. and a keyboard and/or controller 514, which can include a mouse, touch screen, trackball, game controller, voice-recognition device, or any other device that permits a system user to input information into and receive information from the information handling system 500.
• a display device 509 such as a monitor or touch screen
• additional peripheral components 510 such as speakers, etc.
• keyboard and/or controller 514 which can include a mouse, touch screen, trackball, game controller, voice-recognition device, or any other device that permits a system user to input information into and receive information from the information handling system 500.
• the term "horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a substrate, such as a wafer or die, regardless of the orientation of the substrate.
• the term 'Vertical refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the substrate, regardless of the orientation of the substrate.

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