TWI538165B - 包含具有不同的少數載子生命週期之通道區域之裝置及方法 - Google Patents

包含具有不同的少數載子生命週期之通道區域之裝置及方法 Download PDF

Info

Publication number
TWI538165B
TWI538165B TW101129260A TW101129260A TWI538165B TW I538165 B TWI538165 B TW I538165B TW 101129260 A TW101129260 A TW 101129260A TW 101129260 A TW101129260 A TW 101129260A TW I538165 B TWI538165 B TW I538165B
Authority
TW
Taiwan
Prior art keywords
region
forming
type
doped
channel region
Prior art date
Application number
TW101129260A
Other languages
English (en)
Chinese (zh)
Other versions
TW201316489A (zh
Inventor
帕洛 泰莎瑞爾
歐瑞里歐 吉安卡羅 莫瑞
合田晃
趙毅傑
Original Assignee
美光科技公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美光科技公司 filed Critical 美光科技公司
Publication of TW201316489A publication Critical patent/TW201316489A/zh
Application granted granted Critical
Publication of TWI538165B publication Critical patent/TWI538165B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
TW101129260A 2011-08-16 2012-08-13 包含具有不同的少數載子生命週期之通道區域之裝置及方法 TWI538165B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/211,033 US8742481B2 (en) 2011-08-16 2011-08-16 Apparatuses and methods comprising a channel region having different minority carrier lifetimes

Publications (2)

Publication Number Publication Date
TW201316489A TW201316489A (zh) 2013-04-16
TWI538165B true TWI538165B (zh) 2016-06-11

Family

ID=47712018

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101129260A TWI538165B (zh) 2011-08-16 2012-08-13 包含具有不同的少數載子生命週期之通道區域之裝置及方法

Country Status (7)

Country Link
US (2) US8742481B2 (enExample)
EP (1) EP2745321A4 (enExample)
JP (1) JP5877246B2 (enExample)
KR (1) KR102044045B1 (enExample)
CN (1) CN103828049A (enExample)
TW (1) TWI538165B (enExample)
WO (1) WO2013025719A2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8750040B2 (en) 2011-01-21 2014-06-10 Micron Technology, Inc. Memory devices having source lines directly coupled to body regions and methods
US8742481B2 (en) 2011-08-16 2014-06-03 Micron Technology, Inc. Apparatuses and methods comprising a channel region having different minority carrier lifetimes
US9214235B2 (en) * 2013-04-16 2015-12-15 Conversant Intellectual Property Management Inc. U-shaped common-body type cell string
SG10201803464XA (en) 2017-06-12 2019-01-30 Samsung Electronics Co Ltd Semiconductor memory device and method of manufacturing the same
US10727244B2 (en) 2017-06-12 2020-07-28 Samsung Electronics Co., Ltd. Semiconductor memory devices and methods of fabricating the same
US10923493B2 (en) 2018-09-06 2021-02-16 Micron Technology, Inc. Microelectronic devices, electronic systems, and related methods
WO2020076652A1 (en) 2018-10-09 2020-04-16 Micron Technology, Inc. Semiconductor devices comprising transistors having increased threshold voltage and related methods and systems

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07226446A (ja) * 1994-02-12 1995-08-22 Toshiba Corp 半導体装置及びその製造方法
JP4104701B2 (ja) 1997-06-26 2008-06-18 株式会社半導体エネルギー研究所 半導体装置
JP4236722B2 (ja) 1998-02-05 2009-03-11 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6333217B1 (en) * 1999-05-14 2001-12-25 Matsushita Electric Industrial Co., Ltd. Method of forming MOSFET with channel, extension and pocket implants
JP2003031693A (ja) 2001-07-19 2003-01-31 Toshiba Corp 半導体メモリ装置
US7304354B2 (en) * 2004-02-17 2007-12-04 Silicon Space Technology Corp. Buried guard ring and radiation hardened isolation structures and fabrication methods
US20060278913A1 (en) * 2005-06-08 2006-12-14 Micron Technology, Inc. Non-volatile memory cells without diffusion junctions
KR20070009183A (ko) 2005-07-15 2007-01-18 엘지전자 주식회사 팝업기능과 연동하는 알람 방법 및 이를 이용한 이동통신단말기
JP4592580B2 (ja) * 2005-12-19 2010-12-01 株式会社東芝 不揮発性半導体記憶装置
JP4822841B2 (ja) 2005-12-28 2011-11-24 株式会社東芝 半導体記憶装置及びその製造方法
US20080061358A1 (en) * 2006-03-02 2008-03-13 Embedded Memory, Inc. Method of reducing memory cell size for non-volatile memory device
KR20070091833A (ko) 2006-03-07 2007-09-12 삼성전자주식회사 비휘발성 기억 소자 및 그 형성 방법
US20080083943A1 (en) 2006-10-10 2008-04-10 Walker Andrew J Dual-gate memory device and optimization of electrical interaction between front and back gates to enable scaling
KR100876082B1 (ko) * 2006-12-07 2008-12-26 삼성전자주식회사 메모리 소자 및 그 형성 방법
JP4791949B2 (ja) * 2006-12-22 2011-10-12 株式会社東芝 不揮発性半導体メモリ
US7525136B2 (en) * 2007-05-03 2009-04-28 Dsm Solutions, Inc. JFET device with virtual source and drain link regions and method of fabrication
US20100155858A1 (en) * 2007-09-04 2010-06-24 Yuan-Feng Chen Asymmetric extension device
JP2010114369A (ja) * 2008-11-10 2010-05-20 Toshiba Corp 不揮発性半導体記憶装置
JP5364342B2 (ja) * 2008-11-10 2013-12-11 株式会社東芝 不揮発性半導体記憶装置、及びその製造方法
JP2010118530A (ja) 2008-11-13 2010-05-27 Toshiba Corp 不揮発性半導体記憶装置
KR101559549B1 (ko) 2008-12-08 2015-10-13 삼성전자주식회사 모바일 ＳｏＣ 및 모바일 단말기
JP5356005B2 (ja) * 2008-12-10 2013-12-04 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP2010199235A (ja) * 2009-02-24 2010-09-09 Toshiba Corp 不揮発性半導体記憶装置
JP5330027B2 (ja) * 2009-02-25 2013-10-30 株式会社東芝 不揮発性半導体記憶装置、及びその製造方法
KR101532366B1 (ko) 2009-02-25 2015-07-01 삼성전자주식회사 반도체 기억 소자
US20100314678A1 (en) 2009-06-12 2010-12-16 Se-Yun Lim Non-volatile memory device and method for fabricating the same
JP5044624B2 (ja) * 2009-09-25 2012-10-10 株式会社東芝 不揮発性半導体記憶装置
JP2011108921A (ja) 2009-11-19 2011-06-02 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US8395942B2 (en) * 2010-05-17 2013-03-12 Sandisk Technologies Inc. Junctionless TFT NAND flash memory
US8349681B2 (en) * 2010-06-30 2013-01-08 Sandisk Technologies Inc. Ultrahigh density monolithic, three dimensional vertical NAND memory device
US8514620B2 (en) * 2010-11-29 2013-08-20 Micron Technology, Inc. Memory devices having select gates with P type bodies, memory strings having separate source lines and methods
US8750040B2 (en) * 2011-01-21 2014-06-10 Micron Technology, Inc. Memory devices having source lines directly coupled to body regions and methods
JP5330421B2 (ja) * 2011-02-01 2013-10-30 株式会社東芝 不揮発性半導体記憶装置
US8802525B2 (en) * 2011-08-08 2014-08-12 Micron Technology, Inc. Methods of forming charge storage structures including etching diffused regions to form recesses
US8797806B2 (en) * 2011-08-15 2014-08-05 Micron Technology, Inc. Apparatus and methods including source gates
US8742481B2 (en) 2011-08-16 2014-06-03 Micron Technology, Inc. Apparatuses and methods comprising a channel region having different minority carrier lifetimes
US9251907B2 (en) * 2012-04-03 2016-02-02 Micron Technology, Inc. Memory devices and methods of operating memory devices including applying a potential to a source and a select gate between the source and a string of memory cells while performing a program operation on a memory cell in the string
US9171626B2 (en) * 2012-07-30 2015-10-27 Micron Technology, Inc.. Memory devices and programming memory arrays thereof
US9093152B2 (en) * 2012-10-26 2015-07-28 Micron Technology, Inc. Multiple data line memory and methods
US9305654B2 (en) * 2012-12-19 2016-04-05 Intel Corporation Erase and soft program for vertical NAND flash
JP2014187286A (ja) * 2013-03-25 2014-10-02 Toshiba Corp 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
US20130043505A1 (en) 2013-02-21
US9190472B2 (en) 2015-11-17
TW201316489A (zh) 2013-04-16
WO2013025719A2 (en) 2013-02-21
US8742481B2 (en) 2014-06-03
WO2013025719A3 (en) 2013-05-02
EP2745321A4 (en) 2015-04-01
KR20140068061A (ko) 2014-06-05
EP2745321A2 (en) 2014-06-25
KR102044045B1 (ko) 2019-12-02
JP2014522131A (ja) 2014-08-28
CN103828049A (zh) 2014-05-28
US20140264447A1 (en) 2014-09-18
JP5877246B2 (ja) 2016-03-02

Similar Documents

Publication Publication Date Title
TWI538165B (zh) 包含具有不同的少數載子生命週期之通道區域之裝置及方法
US10964638B2 (en) Vertical memory device including common source line structure
US11978731B2 (en) Method to produce a multi-level semiconductor memory device and structure
US10515981B2 (en) Multilevel semiconductor device and structure with memory
TWI523201B (zh) 具有其帶隙低於主體區域之帶隙的連接區域之記憶體裝置
US10998336B2 (en) Integrated structures and NAND memory arrays
US11705205B2 (en) Memory devices having source lines directly coupled to body regions and methods
US20230320057A1 (en) Recessed transistor terminal via jumpers
US11917821B2 (en) Process for a 3-dimensional array of horizontal nor-type memory strings
US12432926B2 (en) Method to produce a 3D multilayer semiconductor device and structure
US20070075353A1 (en) Flash memory structure and method for fabricating the same
CN107516660B (zh) Nand闪存存储单元、nand闪存及其形成方法