CN103828049A - 包含具有不同的少数载流子寿命的沟道区域的设备及方法 - Google Patents

包含具有不同的少数载流子寿命的沟道区域的设备及方法 Download PDF

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Publication number
CN103828049A
CN103828049A CN201280046388.8A CN201280046388A CN103828049A CN 103828049 A CN103828049 A CN 103828049A CN 201280046388 A CN201280046388 A CN 201280046388A CN 103828049 A CN103828049 A CN 103828049A
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CN
China
Prior art keywords
region
forming
type
channel region
doped
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Pending
Application number
CN201280046388.8A
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English (en)
Chinese (zh)
Inventor
保罗·泰萨罗
奥雷柳·贾恩卡洛·毛里
合田晃
赵一杰
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Micron Technology Inc
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Micron Technology Inc
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Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of CN103828049A publication Critical patent/CN103828049A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
CN201280046388.8A 2011-08-16 2012-08-14 包含具有不同的少数载流子寿命的沟道区域的设备及方法 Pending CN103828049A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/211,033 US8742481B2 (en) 2011-08-16 2011-08-16 Apparatuses and methods comprising a channel region having different minority carrier lifetimes
US13/211,033 2011-08-16
PCT/US2012/050796 WO2013025719A2 (en) 2011-08-16 2012-08-14 Apparatuses and methods comprising a channel region having different minority carrier lifetimes

Publications (1)

Publication Number Publication Date
CN103828049A true CN103828049A (zh) 2014-05-28

Family

ID=47712018

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280046388.8A Pending CN103828049A (zh) 2011-08-16 2012-08-14 包含具有不同的少数载流子寿命的沟道区域的设备及方法

Country Status (7)

Country Link
US (2) US8742481B2 (enExample)
EP (1) EP2745321A4 (enExample)
JP (1) JP5877246B2 (enExample)
KR (1) KR102044045B1 (enExample)
CN (1) CN103828049A (enExample)
TW (1) TWI538165B (enExample)
WO (1) WO2013025719A2 (enExample)

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US8750040B2 (en) 2011-01-21 2014-06-10 Micron Technology, Inc. Memory devices having source lines directly coupled to body regions and methods
US9214235B2 (en) * 2013-04-16 2015-12-15 Conversant Intellectual Property Management Inc. U-shaped common-body type cell string
SG10201803464XA (en) 2017-06-12 2019-01-30 Samsung Electronics Co Ltd Semiconductor memory device and method of manufacturing the same
US10727244B2 (en) 2017-06-12 2020-07-28 Samsung Electronics Co., Ltd. Semiconductor memory devices and methods of fabricating the same
US10923493B2 (en) 2018-09-06 2021-02-16 Micron Technology, Inc. Microelectronic devices, electronic systems, and related methods
WO2020076652A1 (en) 2018-10-09 2020-04-16 Micron Technology, Inc. Semiconductor devices comprising transistors having increased threshold voltage and related methods and systems

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Publication number Priority date Publication date Assignee Title
US9190472B2 (en) 2011-08-16 2015-11-17 Micron Technology, Inc. Apparatuses and methods comprising a channel region having different minority carrier lifetimes

Also Published As

Publication number Publication date
US20130043505A1 (en) 2013-02-21
US9190472B2 (en) 2015-11-17
TW201316489A (zh) 2013-04-16
WO2013025719A2 (en) 2013-02-21
US8742481B2 (en) 2014-06-03
WO2013025719A3 (en) 2013-05-02
EP2745321A4 (en) 2015-04-01
KR20140068061A (ko) 2014-06-05
TWI538165B (zh) 2016-06-11
EP2745321A2 (en) 2014-06-25
KR102044045B1 (ko) 2019-12-02
JP2014522131A (ja) 2014-08-28
US20140264447A1 (en) 2014-09-18
JP5877246B2 (ja) 2016-03-02

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