KR102029682B1 - 반도체 장치 및 반도체 패키지 - Google Patents

반도체 장치 및 반도체 패키지 Download PDF

Info

Publication number
KR102029682B1
KR102029682B1 KR1020130027658A KR20130027658A KR102029682B1 KR 102029682 B1 KR102029682 B1 KR 102029682B1 KR 1020130027658 A KR1020130027658 A KR 1020130027658A KR 20130027658 A KR20130027658 A KR 20130027658A KR 102029682 B1 KR102029682 B1 KR 102029682B1
Authority
KR
South Korea
Prior art keywords
chip
memory
soc
output
wide input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020130027658A
Other languages
English (en)
Korean (ko)
Other versions
KR20140112944A (ko
Inventor
김태선
임경묵
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020130027658A priority Critical patent/KR102029682B1/ko
Priority to JP2014027928A priority patent/JP2014182794A/ja
Priority to TW103107328A priority patent/TWI606569B/zh
Priority to NL2012389A priority patent/NL2012389B1/en
Priority to DE102014103186.5A priority patent/DE102014103186B4/de
Priority to CN201410089978.XA priority patent/CN104051410B/zh
Priority to IN712DE2014 priority patent/IN2014DE00712A/en
Priority to US14/211,033 priority patent/US9275688B2/en
Publication of KR20140112944A publication Critical patent/KR20140112944A/ko
Application granted granted Critical
Publication of KR102029682B1 publication Critical patent/KR102029682B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H10W72/248—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Memory System (AREA)
KR1020130027658A 2013-03-15 2013-03-15 반도체 장치 및 반도체 패키지 Expired - Fee Related KR102029682B1 (ko)

Priority Applications (8)

Application Number Priority Date Filing Date Title
KR1020130027658A KR102029682B1 (ko) 2013-03-15 2013-03-15 반도체 장치 및 반도체 패키지
JP2014027928A JP2014182794A (ja) 2013-03-15 2014-02-17 半導体装置及び半導体パッケージ
TW103107328A TWI606569B (zh) 2013-03-15 2014-03-05 半導體元件以及半導體封裝
NL2012389A NL2012389B1 (en) 2013-03-15 2014-03-10 Semiconductor device and semiconductor package.
DE102014103186.5A DE102014103186B4 (de) 2013-03-15 2014-03-11 Halbleitervorrichtung und Halbleiterpackage
CN201410089978.XA CN104051410B (zh) 2013-03-15 2014-03-12 半导体器件和半导体封装
IN712DE2014 IN2014DE00712A (https=) 2013-03-15 2014-03-12
US14/211,033 US9275688B2 (en) 2013-03-15 2014-03-14 Semiconductor device and semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020130027658A KR102029682B1 (ko) 2013-03-15 2013-03-15 반도체 장치 및 반도체 패키지

Publications (2)

Publication Number Publication Date
KR20140112944A KR20140112944A (ko) 2014-09-24
KR102029682B1 true KR102029682B1 (ko) 2019-10-08

Family

ID=50792497

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020130027658A Expired - Fee Related KR102029682B1 (ko) 2013-03-15 2013-03-15 반도체 장치 및 반도체 패키지

Country Status (8)

Country Link
US (1) US9275688B2 (https=)
JP (1) JP2014182794A (https=)
KR (1) KR102029682B1 (https=)
CN (1) CN104051410B (https=)
DE (1) DE102014103186B4 (https=)
IN (1) IN2014DE00712A (https=)
NL (1) NL2012389B1 (https=)
TW (1) TWI606569B (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9324397B1 (en) * 2015-01-16 2016-04-26 Qualcomm Incorporated Common die for supporting different external memory types with minimal packaging complexity
TWI561960B (en) * 2015-11-05 2016-12-11 Sunplus Technology Co Ltd Clock providing system
KR102413441B1 (ko) 2015-11-12 2022-06-28 삼성전자주식회사 반도체 패키지
KR102468698B1 (ko) * 2015-12-23 2022-11-22 에스케이하이닉스 주식회사 메모리 장치
DE102016011750A1 (de) * 2016-09-29 2018-03-29 Ceramtec-Etec Gmbh Datenträger aus Keramik
US11514996B2 (en) * 2017-07-30 2022-11-29 Neuroblade Ltd. Memory-based processors
KR20190087893A (ko) * 2018-01-17 2019-07-25 삼성전자주식회사 클럭을 공유하는 반도체 패키지 및 전자 시스템
TWI856974B (zh) * 2018-09-06 2024-10-01 埃拉德 希提 可變字長存取
US11335383B2 (en) * 2019-05-31 2022-05-17 Micron Technology, Inc. Memory component for a system-on-chip device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100140750A1 (en) * 2008-12-10 2010-06-10 Qualcomm Incorporated Parallel Plane Memory and Processor Coupling in a 3-D Micro-Architectural System
US20110246746A1 (en) * 2010-03-30 2011-10-06 Brent Keeth Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223454A (en) * 1988-01-29 1993-06-29 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US6724084B1 (en) * 1999-02-08 2004-04-20 Rohm Co., Ltd. Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device
US7173877B2 (en) * 2004-09-30 2007-02-06 Infineon Technologies Ag Memory system with two clock lines and a memory device
WO2006067852A1 (ja) * 2004-12-24 2006-06-29 Spansion Llc 同期型記憶装置、およびその制御方法
JP4910512B2 (ja) * 2006-06-30 2012-04-04 富士通セミコンダクター株式会社 半導体装置および半導体装置の製造方法
US8059443B2 (en) 2007-10-23 2011-11-15 Hewlett-Packard Development Company, L.P. Three-dimensional memory module architectures
US20100174858A1 (en) 2009-01-05 2010-07-08 Taiwan Semiconductor Manufacturing Co., Ltd. Extra high bandwidth memory die stack
US8207754B2 (en) 2009-02-24 2012-06-26 Stmicroelectronics International N.V. Architecture for efficient usage of IO
US8174876B2 (en) * 2009-06-19 2012-05-08 Hynix Semiconductor Inc. Fusion memory device embodied with phase change memory devices having different resistance distributions and data processing system using the same
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US8698321B2 (en) 2009-10-07 2014-04-15 Qualcomm Incorporated Vertically stackable dies having chip identifier structures
US8612809B2 (en) 2009-12-31 2013-12-17 Intel Corporation Systems, methods, and apparatuses for stacked memory
US8796863B2 (en) 2010-02-09 2014-08-05 Samsung Electronics Co., Ltd. Semiconductor memory devices and semiconductor packages
KR20110099384A (ko) * 2010-03-02 2011-09-08 삼성전자주식회사 와이드 입출력 반도체 메모리 장치 및 이를 포함하는 반도체 패키지
KR101728067B1 (ko) 2010-09-03 2017-04-18 삼성전자 주식회사 반도체 메모리 장치
KR20120068216A (ko) 2010-12-17 2012-06-27 에스케이하이닉스 주식회사 반도체 집적회로
US8399961B2 (en) * 2010-12-21 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Tuning the efficiency in the transmission of radio-frequency signals using micro-bumps
KR20120079397A (ko) * 2011-01-04 2012-07-12 삼성전자주식회사 적층형 반도체 장치 및 이의 제조 방법
US8564111B2 (en) * 2011-01-27 2013-10-22 Siano Mobile Silicon Ltd. Stacked digital/RF system-on-chip with integral isolation layer
KR20120098096A (ko) 2011-02-28 2012-09-05 에스케이하이닉스 주식회사 반도체 집적회로
JP5286382B2 (ja) * 2011-04-11 2013-09-11 株式会社日立製作所 半導体装置およびその製造方法
CN102891114B (zh) * 2012-10-24 2015-01-28 上海新储集成电路有限公司 一种上下堆叠的片上系统芯片的制作方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100140750A1 (en) * 2008-12-10 2010-06-10 Qualcomm Incorporated Parallel Plane Memory and Processor Coupling in a 3-D Micro-Architectural System
US20110246746A1 (en) * 2010-03-30 2011-10-06 Brent Keeth Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same

Also Published As

Publication number Publication date
DE102014103186A1 (de) 2014-09-18
JP2014182794A (ja) 2014-09-29
DE102014103186B4 (de) 2021-05-27
TW201436165A (zh) 2014-09-16
KR20140112944A (ko) 2014-09-24
US20140268979A1 (en) 2014-09-18
NL2012389B1 (en) 2016-07-15
US9275688B2 (en) 2016-03-01
CN104051410B (zh) 2018-05-01
CN104051410A (zh) 2014-09-17
NL2012389A (en) 2014-09-16
TWI606569B (zh) 2017-11-21
IN2014DE00712A (https=) 2015-06-19

Similar Documents

Publication Publication Date Title
KR102029682B1 (ko) 반도체 장치 및 반도체 패키지
CN105633063B (zh) 半导体封装件
US10096577B2 (en) Semiconductor memory package including stacked layers and memory device and semiconductor memory system having the same
US10090252B2 (en) Package-on-package type semiconductor device including fan-out memory package
JP6847863B2 (ja) パッケージオンパッケージ構造体用のインターポーザ
JP6760627B2 (ja) カルコゲナイドガラス組成物およびカルコゲナイドスイッチデバイス
US8710655B2 (en) Die packages and systems having the die packages
US9755503B2 (en) Semiconductor device for controlling power-up sequences
US20150311182A1 (en) Semiconductor package and method for manufacturing the same
US20110309468A1 (en) Semiconductor chip package and method of manufacturing the same
US9478502B2 (en) Device identification assignment and total device number detection
US20130099235A1 (en) Semiconductor wafer and method for manufacturing stack package using the same
KR102236572B1 (ko) 반도체 메모리 및 이를 이용한 반도체 시스템
US9804914B2 (en) Semiconductor memory and semiconductor system using the same
US8803327B2 (en) Semiconductor package
US20140014958A1 (en) Semiconductor chip module and semiconductor package having the same
WO2017052767A1 (en) Packaged integrated circuit device with cantilever structure
US10553567B2 (en) Chip stack packages
US20140097513A1 (en) Package-on-Package Type Package Including Integrated Circuit Devices and Associated Passive Components on Different Levels
US9620492B2 (en) Package-on-package type stack package and method for manufacturing the same

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20221002

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20221002

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000