JP6847863B2 - パッケージオンパッケージ構造体用のインターポーザ - Google Patents
パッケージオンパッケージ構造体用のインターポーザ Download PDFInfo
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- JP6847863B2 JP6847863B2 JP2017563204A JP2017563204A JP6847863B2 JP 6847863 B2 JP6847863 B2 JP 6847863B2 JP 2017563204 A JP2017563204 A JP 2017563204A JP 2017563204 A JP2017563204 A JP 2017563204A JP 6847863 B2 JP6847863 B2 JP 6847863B2
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
本出願は、参照により内容全体が本明細書に明確に組み込まれる、同一出願人が所有する2015年6月8日に出願した米国特許出願第14/733201号の優先権を主張する。
102 メモリチップ、メモリデバイス
104 第1のダイ
106 第2のダイ
108 感光性画定可能モールド
110 アンダーフィル
114 下部インターポーザ
120 シリコン基板
122 アンダーフィル
124 パッケージ基板
170 メモリチップの下部パッド
172 感光性画定可能モールドの上部パッド
174 マイクロバンプ
176 銅充填ビア
178 感光性画定可能モールドの下部パッド
180 バリア/シード堆積層
182 銅充填ビア
184 下部インターポーザの上部パッド
186 第1のダイの下部パッド
188 マイクロバンプ
190 第2のダイの下部パッド
192 マイクロバンプ
194 銅充填ビア
196 パッド
198 マイクロバンプ
202 一時的のり
204 一時的担体
206 感光性レジスト層
400 ワイヤレス通信デバイス
410 プロセッサ
422 システムインパッケージデバイス、システムオンチップデバイス
426 ディスプレイコントローラ
428 ディスプレイ
430 入力デバイス
432 メモリ
434 コーダ/デコーダ、コーデック
436 スピーカ
438 マイクロフォン
440 ワイヤレスインターフェース
442 アンテナ
444 電源
446 トランシーバ
490 メモリデバイス
500 製造プロセス
502 物理デバイス情報
504 ユーザインターフェース
506 研究コンピュータ
508 プロセッサ
510 メモリ
512 ライブラリファイル
514 設計コンピュータ
516 プロセッサ
518 メモリ
520 電子設計オートメーション(EDA)ツール
522 回路設計情報
524 ユーザインターフェース
528 製造プロセス
530 マスク製造者
532 マスク
533 ウエハ
534 プロセッサ
535 メモリ
536 ダイ
538 パッケージングプロセス
540 パッケージ
542 PCB設計情報
544 ユーザインターフェース
546 コンピュータ
548 プロセッサ
550 メモリ
552 GERBERファイル
554 基板組立プロセス
556 PCB
558 プリント回路アセンブリ(PCA)
560 製品製造者
562 第1の電子デバイス
564 第2の電子デバイス
Claims (19)
- 第1のダイと、
第2のダイと、
前記第1のダイと前記第2のダイとの間のモールドであって、前記モールドがバリア/シード堆積層および銅を含むビアを含み、前記バリア/シード堆積層が前記銅を前記モールドから絶縁するように構成される、モールドと、
前記ビアによって前記第1のダイおよび前記第2のダイに電気的に結合するように構成されたメモリデバイスと
を備える、パッケージオンパッケージ(PoP)構造体であって、
前記モールドが感光性誘電体モールドを備える、PoP構造体。 - 前記ビアが、
前記メモリデバイスと前記第1のダイとの間で第1の電気信号を転送することと、
前記メモリデバイスと前記第2のダイとの間で第2の電気信号を転送することと
を行うように構成される、請求項1に記載のPoP構造体。 - 前記ビアに電気的に結合するように構成された下部インターポーザであって、前記第1の電気信号が前記下部インターポーザを介して前記メモリデバイスと前記第1のダイとの間で転送され、前記第2の電気信号が前記下部インターポーザを介して前記メモリデバイスと前記第2のダイとの間で転送される、下部インターポーザをさらに備える、請求項2に記載のPoP構造体。
- 前記メモリデバイスが、ワイド入出力(I/O)メモリデバイスを含む、請求項1に記載のPoP構造体。
- 前記ワイドI/Oメモリデバイスが、約1700個から2000個の間のI/Oポートを含む、請求項4に記載のPoP構造体。
- 前記メモリデバイスが前記PoP構造体の第1のパッケージに含まれる、請求項1に記載のPoP構造体。
- 前記第1のダイ、前記第2のダイ、および前記ビアが前記PoP構造体の第2のパッケージに含まれる、請求項1に記載のPoP構造体。
- 前記第1のダイ、前記第2のダイ、前記メモリデバイス、および前記ビアが、ワイヤレスデバイス、通信デバイス、携帯情報端末(PDA)、ナビゲーションデバイス、音楽プレーヤ、ビデオプレーヤ、エンターテインメントユニット、固定位置データユニット、およびコンピュータに統合される、請求項1に記載のPoP構造体。
- パッケージオンパッケージ(PoP)構造体を形成するための方法であって、
第1のダイおよび第2のダイを下部インターポーザに結合するステップと、
前記第1のダイ、前記第2のダイ、および前記下部インターポーザ上にモールドを形成するステップと、
前記モールド内に1つまたは複数のビアをエッチングするステップであって、前記1つまたは複数のビアが前記第1のダイと前記第2のダイとの間に配置される、ステップと、
前記1つまたは複数のビアを銅で充填する前に前記1つまたは複数のビア内にバリア/シード堆積層を堆積するステップと、
1つまたは複数のビアを有するインターポーザを形成するために前記1つまたは複数のビアを銅で充填するステップと
を備える、方法。 - 前記モールドが感光性誘電体モールドを備える、請求項9に記載の方法。
- 前記1つまたは複数のビアが前記下部インターポーザに電気的に結合され、前記下部インターポーザが前記第1のダイおよび前記第2のダイに電気的に結合される、請求項9に記載の方法。
- 前記第1のダイ、前記第2のダイ、および前記インターポーザにメモリデバイスを結合するステップであって、前記インターポーザが前記メモリデバイスと前記第1のダイまたは前記第2のダイのうちの少なくとも1つとの間で電気信号を転送するように構成される、ステップをさらに備える、請求項9に記載の方法。
- 前記PoP構造体が、前記インターポーザ、前記第1のダイ、前記第2のダイ、前記下部インターポーザ、および前記メモリデバイスを備える、請求項12に記載の方法。
- 前記メモリデバイスが、ワイド入出力(I/O)メモリデバイスを含む、請求項12に記載の方法。
- 前記ワイドI/Oメモリデバイスが、約1700個から2000個の間のI/Oポートを含む、請求項14に記載の方法。
- 前記メモリデバイスが、前記PoP構造体の第1のパッケージに含まれる、請求項12に記載の方法。
- 前記第1のダイ、前記第2のダイ、および前記インターポーザが前記PoP構造体の第2のパッケージに含まれる、請求項16に記載の方法。
- 前記第1のダイおよび前記第2のダイを前記下部インターポーザ上に結合するステップが製造機器を使用して実行され、前記モールドを形成するステップが、前記製造機器を使用して実行され、前記1つまたは複数のビアをエッチングするステップが、前記製造機器を使用して実行され、前記1つまたは複数のビアを前記銅で充填するステップが、前記製造機器を使用して実行される、請求項9に記載の方法。
- 第1の論理機能を実行するための手段と、
第2の論理機能を実行するための手段と、
前記第1の論理機能を実行するための前記手段と前記第2の論理機能を実行するための前記手段とに結合された、データを記憶するための手段と、
データを記憶するための前記手段と、前記第1の論理機能を実行するための前記手段または前記第2の論理機能を実行するための前記手段のうちの少なくとも1つとの間で電気信号を転送するための手段であって、電気信号を転送するための前記手段が、前記第1の論理機能を実行するための前記手段と、前記第2の論理機能を実行するための前記手段との間に存在し、モールド内に形成されたビアを備え、ここで、前記ビアがバリア/シード堆積層および銅を含み、前記バリア/シード堆積層が前記銅を前記モールドから絶縁するように構成される、電気信号を転送するための手段と
を備える、パッケージオンパッケージ(PoP)構造体であって、
前記モールドが感光性誘電体モールドを備える、PoP構造体。
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US14/733,201 US9613942B2 (en) | 2015-06-08 | 2015-06-08 | Interposer for a package-on-package structure |
US14/733,201 | 2015-06-08 | ||
PCT/US2016/033948 WO2016200604A1 (en) | 2015-06-08 | 2016-05-24 | Interposer for a package-on-package structure |
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JP2018518057A JP2018518057A (ja) | 2018-07-05 |
JP6847863B2 true JP6847863B2 (ja) | 2021-03-24 |
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BR112017026386B1 (pt) | 2023-02-07 |
BR112017026386A2 (ja) | 2018-08-21 |
US20160358899A1 (en) | 2016-12-08 |
KR102550873B1 (ko) | 2023-07-03 |
CN107690700B (zh) | 2022-01-11 |
KR20180016384A (ko) | 2018-02-14 |
US9613942B2 (en) | 2017-04-04 |
CA2985197C (en) | 2023-09-26 |
CN107690700A (zh) | 2018-02-13 |
EP3304593A1 (en) | 2018-04-11 |
CA2985197A1 (en) | 2016-12-15 |
WO2016200604A1 (en) | 2016-12-15 |
JP2018518057A (ja) | 2018-07-05 |
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