KR101965375B1 - 저 전력 아키텍처들 - Google Patents

저 전력 아키텍처들 Download PDF

Info

Publication number
KR101965375B1
KR101965375B1 KR1020157027799A KR20157027799A KR101965375B1 KR 101965375 B1 KR101965375 B1 KR 101965375B1 KR 1020157027799 A KR1020157027799 A KR 1020157027799A KR 20157027799 A KR20157027799 A KR 20157027799A KR 101965375 B1 KR101965375 B1 KR 101965375B1
Authority
KR
South Korea
Prior art keywords
voltage
low
clock signal
clock
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020157027799A
Other languages
English (en)
Korean (ko)
Other versions
KR20150129789A (ko
Inventor
마이클 조셉 브루놀리
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20150129789A publication Critical patent/KR20150129789A/ko
Application granted granted Critical
Publication of KR101965375B1 publication Critical patent/KR101965375B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037Bistable circuits
    • H03K3/0375Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details
    • H03K3/012Modifications of generator to improve response time or to decrease power consumption
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356104Bistable circuits using complementary field-effect transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits

Landscapes

  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Power Sources (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1020157027799A 2013-03-15 2014-03-14 저 전력 아키텍처들 Active KR101965375B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361800116P 2013-03-15 2013-03-15
US61/800,116 2013-03-15
US14/213,907 US9184733B2 (en) 2013-03-15 2014-03-14 Low power architectures
PCT/US2014/029721 WO2014145066A2 (en) 2013-03-15 2014-03-14 Low power architectures
US14/213,907 2014-03-14

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR1020197008612A Division KR101970612B1 (ko) 2013-03-15 2014-03-14 저 전력 아키텍처들

Publications (2)

Publication Number Publication Date
KR20150129789A KR20150129789A (ko) 2015-11-20
KR101965375B1 true KR101965375B1 (ko) 2019-04-03

Family

ID=51524865

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1020157027799A Active KR101965375B1 (ko) 2013-03-15 2014-03-14 저 전력 아키텍처들
KR1020197008612A Active KR101970612B1 (ko) 2013-03-15 2014-03-14 저 전력 아키텍처들

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1020197008612A Active KR101970612B1 (ko) 2013-03-15 2014-03-14 저 전력 아키텍처들

Country Status (8)

Country Link
US (2) US9184733B2 (enExample)
EP (1) EP2974018B1 (enExample)
JP (2) JP6262330B2 (enExample)
KR (2) KR101965375B1 (enExample)
CN (2) CN105144579B (enExample)
ES (1) ES2706477T3 (enExample)
HU (1) HUE042764T2 (enExample)
WO (1) WO2014145066A2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101965375B1 (ko) 2013-03-15 2019-04-03 퀄컴 인코포레이티드 저 전력 아키텍처들
US10120967B2 (en) * 2014-07-25 2018-11-06 Plsense Ltd. Methods and apparatuses for SW programmable adaptive bias control for speed and yield improvement in the near/sub-threshold domain
US9768775B2 (en) * 2014-10-30 2017-09-19 Plsense Ltd. Methods and apparatuses for sub-threhold clock tree design for optimal power
US9355696B1 (en) * 2014-11-06 2016-05-31 Xilinx, Inc. Calibration in a control device receiving from a source synchronous interface
US9712141B2 (en) * 2015-12-03 2017-07-18 Apple Inc. Modulation of power supply voltage for varying propagation delay
KR102491690B1 (ko) * 2016-08-17 2023-01-26 에스케이하이닉스 주식회사 클락 검출기 및 클락 검출 방법
US10411910B2 (en) * 2016-11-23 2019-09-10 DeGirum Corporation Distributed control synchronized ring network architecture
US10352997B2 (en) 2017-08-03 2019-07-16 Samsung Electronics Co., Ltd. Method of measuring clock jitter, clock jitter measurement circuit, and semiconductor device including the same
CN107733402B (zh) * 2017-10-18 2020-10-30 东南大学 面向近阈值低电压的时序监测单元及监测系统
CN115328255A (zh) * 2022-09-11 2022-11-11 北京工业大学 一种基于电压比较器的低功耗轻重负载转换ldo电路
US20250015715A1 (en) * 2023-07-05 2025-01-09 Cirrus Logic International Semiconductor Ltd. Switched-capacitor battery management power supply providing power from portions of a multi-cell battery

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2863453B2 (ja) * 1994-01-19 1999-03-03 松下電器産業株式会社 半導体集積回路の設計方法及び論理合成方法
US5568429A (en) 1995-07-05 1996-10-22 Sun Microsystems, Inc. Low power data latch with overdriven clock signals
US5646557A (en) * 1995-07-31 1997-07-08 International Business Machines Corporation Data processing system and method for improving performance of domino-type logic using multiphase clocks
JP3562060B2 (ja) * 1995-09-29 2004-09-08 株式会社デンソー 半導体集積回路装置
US6252418B1 (en) * 1999-03-31 2001-06-26 International Business Machines Corporation Reduced area active above-supply and below-ground noise suppression circuits
JP3327249B2 (ja) * 1999-05-11 2002-09-24 日本電気株式会社 Pll回路
US6570227B2 (en) * 1999-06-23 2003-05-27 Bae Systems Information And Electronics Systems Integration, Inc. High-performance high-density CMOS SRAM cell
US6587907B1 (en) * 2000-05-01 2003-07-01 Hewlett-Packard Development Company, L.P. System and method for generating a clock delay within an interconnect cable assembly
JP3632151B2 (ja) * 2000-06-06 2005-03-23 日本電信電話株式会社 断熱充電レジスタ回路
JP3418712B2 (ja) * 2000-09-29 2003-06-23 富士通カンタムデバイス株式会社 位相比較回路
JP3630092B2 (ja) * 2000-10-19 2005-03-16 日本電気株式会社 位相周波数比較回路
JP3614125B2 (ja) 2000-10-23 2005-01-26 三星電子株式会社 Cpフリップフロップ
KR100400042B1 (ko) * 2000-10-23 2003-09-29 삼성전자주식회사 Cp 플립플롭
JP4754159B2 (ja) * 2001-02-16 2011-08-24 富士通株式会社 データ伝送速度の1/2周波数クロックを用いる光受信機のタイミング抽出回路及び光送受信機のデューティずれ対応回路
JP4137528B2 (ja) * 2002-06-13 2008-08-20 セイコーインスツル株式会社 電源変換回路
CN2684433Y (zh) * 2003-05-05 2005-03-09 X-L新纳基有限责任公司 一种配电系统中的导线漏电检测及断路装置
JP3776895B2 (ja) * 2003-05-14 2006-05-17 沖電気工業株式会社 位相調整回路
US7486702B1 (en) * 2003-08-11 2009-02-03 Cisco Technology, Inc DDR interface for reducing SSO/SSI noise
KR101045295B1 (ko) * 2004-04-29 2011-06-29 삼성전자주식회사 Mtcmos 플립-플롭, 그를 포함하는 mtcmos회로, 및 그 생성 방법
JP2006074631A (ja) * 2004-09-03 2006-03-16 Koninkl Philips Electronics Nv レベルシフタ及び電圧変換装置
US7173494B2 (en) * 2005-01-20 2007-02-06 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and system for operating a feedback system for a voltage controlled oscillator that involves correcting for offset related to the feedback system
KR100670682B1 (ko) 2005-02-04 2007-01-17 주식회사 하이닉스반도체 반도체 기억 소자에서의 데이터 출력 회로 및 방법
US7420403B2 (en) * 2005-12-08 2008-09-02 Electronics And Telecommunications Research Institute Latch circuit and flip-flop
CN101098116B (zh) * 2006-06-30 2010-06-16 比亚迪股份有限公司 一种直流无刷电机的模拟无级调速方法
JP2008166910A (ja) * 2006-12-27 2008-07-17 Matsushita Electric Ind Co Ltd クロック信号生成装置及びアナログ−デジタル変換装置
US20080258790A1 (en) * 2007-04-17 2008-10-23 Texas Instruments Incorporated Systems and Devices for Sub-threshold Data Capture
GB0708324D0 (en) 2007-04-30 2007-06-06 Univ Catholique Louvain Ultra-low-power circuit
KR100896188B1 (ko) * 2007-05-25 2009-05-12 삼성전자주식회사 레벨 변환 플립-플롭, 및 레벨 변환 플립-플롭의 동작 방법
JP2009070980A (ja) * 2007-09-12 2009-04-02 Sony Corp 半導体集積回路
US8103898B2 (en) * 2008-01-04 2012-01-24 Micron Technology, Inc. Explicit skew interface for mitigating crosstalk and simultaneous switching noise
US8212541B2 (en) * 2008-05-08 2012-07-03 Massachusetts Institute Of Technology Power converter with capacitive energy transfer and fast dynamic response
US7671654B2 (en) * 2008-06-27 2010-03-02 Freescale Semiconductor, Inc. Device having clock generating capabilities and a method for generating a clock signal
US8416587B2 (en) * 2008-11-20 2013-04-09 Silergy Technology Synchronous rectifier control circuits and methods of controlling synchronous rectifiers
KR101375466B1 (ko) * 2009-01-12 2014-03-18 램버스 인코포레이티드 다중 전력 모드를 갖는 메조크로노스 시그널링 시스템
JP2012516629A (ja) * 2009-01-27 2012-07-19 アギア システムズ インコーポレーテッド 性能監視用クリティカルパス回路
JP4791581B2 (ja) * 2009-08-01 2011-10-12 株式会社半導体理工学研究センター サブスレッショルドディジタルcmos回路のための電源電圧制御回路及び制御方法
CN102044966B (zh) * 2009-10-26 2013-01-09 立锜科技股份有限公司 具有自适应电压位置控制的电源转换器控制电路及其控制方法
JP2011135297A (ja) * 2009-12-24 2011-07-07 Panasonic Corp フリップフロップ回路及び分周回路
CN101841901B (zh) * 2009-12-30 2013-01-02 中国科学院电子学研究所 射频信道闭环自动增益控制装置及方法
JP2012165606A (ja) * 2011-02-09 2012-08-30 Handotai Rikougaku Kenkyu Center:Kk 電源装置
JP5724775B2 (ja) * 2011-09-12 2015-05-27 ソニー株式会社 集積回路
US8633753B2 (en) * 2012-02-09 2014-01-21 Analog Devices, Inc. Clock distribution system and method for a multi-bit latch
JP2014140100A (ja) * 2013-01-21 2014-07-31 Sony Corp 位相比較回路及びデータ受信装置
KR101965375B1 (ko) 2013-03-15 2019-04-03 퀄컴 인코포레이티드 저 전력 아키텍처들

Also Published As

Publication number Publication date
EP2974018A2 (en) 2016-01-20
CN107302350A (zh) 2017-10-27
KR20190033665A (ko) 2019-03-29
ES2706477T3 (es) 2019-03-29
CN105144579B (zh) 2018-06-01
CN105144579A (zh) 2015-12-09
US9595944B2 (en) 2017-03-14
KR20150129789A (ko) 2015-11-20
US20140266369A1 (en) 2014-09-18
WO2014145066A2 (en) 2014-09-18
HUE042764T2 (hu) 2019-07-29
JP6262330B2 (ja) 2018-01-17
JP2016521400A (ja) 2016-07-21
JP2018077871A (ja) 2018-05-17
EP2974018B1 (en) 2018-11-21
KR101970612B1 (ko) 2019-08-13
US9184733B2 (en) 2015-11-10
WO2014145066A3 (en) 2014-11-06
CN107302350B (zh) 2020-11-27
US20160013775A1 (en) 2016-01-14
JP6517312B2 (ja) 2019-05-22

Similar Documents

Publication Publication Date Title
KR101965375B1 (ko) 저 전력 아키텍처들
US20100176892A1 (en) Ultra Low Power Oscillator
Wei et al. A low power switching power supply for self-clocked systems
Lee et al. A constant energy-per-cycle ring oscillator over a wide frequency range for wireless sensor nodes
US5781062A (en) Semiconductor integrated circuit
US8884687B2 (en) Power gating circuit
US8791717B2 (en) Asynchronous-logic circuit for full dynamic voltage control
US9876486B2 (en) Clock gated flip-flop
CN101529723B (zh) 具有电容器比值可选工作周期的和到s-r锁存器的单输入亚阈值导电比较器的低压振荡器
US8884669B2 (en) Electronic device with power mode control buffers
US8854086B1 (en) Clock distribution systems for low power applications
US7795917B2 (en) High-speed buffer circuit, system and method
US6650152B2 (en) Intermediate voltage control circuit having reduced power consumption
KR20010047535A (ko) 펄스 발생기
Mal et al. Non Overlapping Clock (NOC) generator for low frequency switched capacitor circuits
US10855257B2 (en) Pulsed latch system with state retention and method of operation
CN106160726B (zh) 电压电平移位器
Katare et al. An Adaptive Feedback High Voltage Resilient Floating and Full-Scale Level-Shifter
JP2004328064A (ja) クロック回路

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20151006

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20181206

Comment text: Request for Examination of Application

PA0302 Request for accelerated examination

Patent event date: 20181206

Patent event code: PA03022R01D

Comment text: Request for Accelerated Examination

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20181217

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20190306

A107 Divisional application of patent
PA0104 Divisional application for international application

Comment text: Divisional Application for International Patent

Patent event code: PA01041R01D

Patent event date: 20190325

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20190328

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20190328

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20211229

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20240102

Start annual number: 6

End annual number: 6