ES2706477T3 - Arquitecturas de baja potencia - Google Patents
Arquitecturas de baja potencia Download PDFInfo
- Publication number
- ES2706477T3 ES2706477T3 ES14723581T ES14723581T ES2706477T3 ES 2706477 T3 ES2706477 T3 ES 2706477T3 ES 14723581 T ES14723581 T ES 14723581T ES 14723581 T ES14723581 T ES 14723581T ES 2706477 T3 ES2706477 T3 ES 2706477T3
- Authority
- ES
- Spain
- Prior art keywords
- voltage
- clock
- clock signal
- flop
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000010355 oscillation Effects 0.000 claims abstract description 10
- 230000001902 propagating effect Effects 0.000 claims abstract description 7
- 239000003990 capacitor Substances 0.000 claims description 62
- 238000000034 method Methods 0.000 claims description 22
- 230000000903 blocking effect Effects 0.000 claims description 11
- 230000008878 coupling Effects 0.000 claims description 5
- 238000010168 coupling process Methods 0.000 claims description 5
- 238000005859 coupling reaction Methods 0.000 claims description 5
- 238000007599 discharging Methods 0.000 claims description 2
- 238000012360 testing method Methods 0.000 description 36
- 238000012546 transfer Methods 0.000 description 26
- 239000000872 buffer Substances 0.000 description 20
- 230000001934 delay Effects 0.000 description 9
- 230000003111 delayed effect Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- 230000000295 complement effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000644 propagated effect Effects 0.000 description 3
- 230000003213 activating effect Effects 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000001174 ascending effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
Landscapes
- Logic Circuits (AREA)
- Manipulation Of Pulses (AREA)
- Power Sources (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361800116P | 2013-03-15 | 2013-03-15 | |
| PCT/US2014/029721 WO2014145066A2 (en) | 2013-03-15 | 2014-03-14 | Low power architectures |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ES2706477T3 true ES2706477T3 (es) | 2019-03-29 |
Family
ID=51524865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES14723581T Active ES2706477T3 (es) | 2013-03-15 | 2014-03-14 | Arquitecturas de baja potencia |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US9184733B2 (enExample) |
| EP (1) | EP2974018B1 (enExample) |
| JP (2) | JP6262330B2 (enExample) |
| KR (2) | KR101965375B1 (enExample) |
| CN (2) | CN105144579B (enExample) |
| ES (1) | ES2706477T3 (enExample) |
| HU (1) | HUE042764T2 (enExample) |
| WO (1) | WO2014145066A2 (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101965375B1 (ko) | 2013-03-15 | 2019-04-03 | 퀄컴 인코포레이티드 | 저 전력 아키텍처들 |
| US10120967B2 (en) * | 2014-07-25 | 2018-11-06 | Plsense Ltd. | Methods and apparatuses for SW programmable adaptive bias control for speed and yield improvement in the near/sub-threshold domain |
| US9768775B2 (en) * | 2014-10-30 | 2017-09-19 | Plsense Ltd. | Methods and apparatuses for sub-threhold clock tree design for optimal power |
| US9355696B1 (en) * | 2014-11-06 | 2016-05-31 | Xilinx, Inc. | Calibration in a control device receiving from a source synchronous interface |
| US9712141B2 (en) * | 2015-12-03 | 2017-07-18 | Apple Inc. | Modulation of power supply voltage for varying propagation delay |
| KR102491690B1 (ko) * | 2016-08-17 | 2023-01-26 | 에스케이하이닉스 주식회사 | 클락 검출기 및 클락 검출 방법 |
| US10411910B2 (en) * | 2016-11-23 | 2019-09-10 | DeGirum Corporation | Distributed control synchronized ring network architecture |
| US10352997B2 (en) | 2017-08-03 | 2019-07-16 | Samsung Electronics Co., Ltd. | Method of measuring clock jitter, clock jitter measurement circuit, and semiconductor device including the same |
| CN107733402B (zh) * | 2017-10-18 | 2020-10-30 | 东南大学 | 面向近阈值低电压的时序监测单元及监测系统 |
| CN115328255A (zh) * | 2022-09-11 | 2022-11-11 | 北京工业大学 | 一种基于电压比较器的低功耗轻重负载转换ldo电路 |
| US20250015715A1 (en) * | 2023-07-05 | 2025-01-09 | Cirrus Logic International Semiconductor Ltd. | Switched-capacitor battery management power supply providing power from portions of a multi-cell battery |
Family Cites Families (44)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2863453B2 (ja) * | 1994-01-19 | 1999-03-03 | 松下電器産業株式会社 | 半導体集積回路の設計方法及び論理合成方法 |
| US5568429A (en) | 1995-07-05 | 1996-10-22 | Sun Microsystems, Inc. | Low power data latch with overdriven clock signals |
| US5646557A (en) * | 1995-07-31 | 1997-07-08 | International Business Machines Corporation | Data processing system and method for improving performance of domino-type logic using multiphase clocks |
| JP3562060B2 (ja) * | 1995-09-29 | 2004-09-08 | 株式会社デンソー | 半導体集積回路装置 |
| US6252418B1 (en) * | 1999-03-31 | 2001-06-26 | International Business Machines Corporation | Reduced area active above-supply and below-ground noise suppression circuits |
| JP3327249B2 (ja) * | 1999-05-11 | 2002-09-24 | 日本電気株式会社 | Ｐｌｌ回路 |
| US6570227B2 (en) * | 1999-06-23 | 2003-05-27 | Bae Systems Information And Electronics Systems Integration, Inc. | High-performance high-density CMOS SRAM cell |
| US6587907B1 (en) * | 2000-05-01 | 2003-07-01 | Hewlett-Packard Development Company, L.P. | System and method for generating a clock delay within an interconnect cable assembly |
| JP3632151B2 (ja) * | 2000-06-06 | 2005-03-23 | 日本電信電話株式会社 | 断熱充電レジスタ回路 |
| JP3418712B2 (ja) * | 2000-09-29 | 2003-06-23 | 富士通カンタムデバイス株式会社 | 位相比較回路 |
| JP3630092B2 (ja) * | 2000-10-19 | 2005-03-16 | 日本電気株式会社 | 位相周波数比較回路 |
| JP3614125B2 (ja) | 2000-10-23 | 2005-01-26 | 三星電子株式会社 | Ｃｐフリップフロップ |
| KR100400042B1 (ko) * | 2000-10-23 | 2003-09-29 | 삼성전자주식회사 | Ｃｐ 플립플롭 |
| JP4754159B2 (ja) * | 2001-02-16 | 2011-08-24 | 富士通株式会社 | データ伝送速度の１／２周波数クロックを用いる光受信機のタイミング抽出回路及び光送受信機のデューティずれ対応回路 |
| JP4137528B2 (ja) * | 2002-06-13 | 2008-08-20 | セイコーインスツル株式会社 | 電源変換回路 |
| CN2684433Y (zh) * | 2003-05-05 | 2005-03-09 | X-L新纳基有限责任公司 | 一种配电系统中的导线漏电检测及断路装置 |
| JP3776895B2 (ja) * | 2003-05-14 | 2006-05-17 | 沖電気工業株式会社 | 位相調整回路 |
| US7486702B1 (en) * | 2003-08-11 | 2009-02-03 | Cisco Technology, Inc | DDR interface for reducing SSO/SSI noise |
| KR101045295B1 (ko) * | 2004-04-29 | 2011-06-29 | 삼성전자주식회사 | Ｍｔｃｍｏｓ 플립-플롭, 그를 포함하는 ｍｔｃｍｏｓ회로, 및 그 생성 방법 |
| JP2006074631A (ja) * | 2004-09-03 | 2006-03-16 | Koninkl Philips Electronics Nv | レベルシフタ及び電圧変換装置 |
| US7173494B2 (en) * | 2005-01-20 | 2007-02-06 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Method and system for operating a feedback system for a voltage controlled oscillator that involves correcting for offset related to the feedback system |
| KR100670682B1 (ko) | 2005-02-04 | 2007-01-17 | 주식회사 하이닉스반도체 | 반도체 기억 소자에서의 데이터 출력 회로 및 방법 |
| US7420403B2 (en) * | 2005-12-08 | 2008-09-02 | Electronics And Telecommunications Research Institute | Latch circuit and flip-flop |
| CN101098116B (zh) * | 2006-06-30 | 2010-06-16 | 比亚迪股份有限公司 | 一种直流无刷电机的模拟无级调速方法 |
| JP2008166910A (ja) * | 2006-12-27 | 2008-07-17 | Matsushita Electric Ind Co Ltd | クロック信号生成装置及びアナログ−デジタル変換装置 |
| US20080258790A1 (en) * | 2007-04-17 | 2008-10-23 | Texas Instruments Incorporated | Systems and Devices for Sub-threshold Data Capture |
| GB0708324D0 (en) | 2007-04-30 | 2007-06-06 | Univ Catholique Louvain | Ultra-low-power circuit |
| KR100896188B1 (ko) * | 2007-05-25 | 2009-05-12 | 삼성전자주식회사 | 레벨 변환 플립-플롭, 및 레벨 변환 플립-플롭의 동작 방법 |
| JP2009070980A (ja) * | 2007-09-12 | 2009-04-02 | Sony Corp | 半導体集積回路 |
| US8103898B2 (en) * | 2008-01-04 | 2012-01-24 | Micron Technology, Inc. | Explicit skew interface for mitigating crosstalk and simultaneous switching noise |
| US8212541B2 (en) * | 2008-05-08 | 2012-07-03 | Massachusetts Institute Of Technology | Power converter with capacitive energy transfer and fast dynamic response |
| US7671654B2 (en) * | 2008-06-27 | 2010-03-02 | Freescale Semiconductor, Inc. | Device having clock generating capabilities and a method for generating a clock signal |
| US8416587B2 (en) * | 2008-11-20 | 2013-04-09 | Silergy Technology | Synchronous rectifier control circuits and methods of controlling synchronous rectifiers |
| KR101375466B1 (ko) * | 2009-01-12 | 2014-03-18 | 램버스 인코포레이티드 | 다중 전력 모드를 갖는 메조크로노스 시그널링 시스템 |
| JP2012516629A (ja) * | 2009-01-27 | 2012-07-19 | アギア システムズ インコーポレーテッド | 性能監視用クリティカルパス回路 |
| JP4791581B2 (ja) * | 2009-08-01 | 2011-10-12 | 株式会社半導体理工学研究センター | サブスレッショルドディジタルｃｍｏｓ回路のための電源電圧制御回路及び制御方法 |
| CN102044966B (zh) * | 2009-10-26 | 2013-01-09 | 立锜科技股份有限公司 | 具有自适应电压位置控制的电源转换器控制电路及其控制方法 |
| JP2011135297A (ja) * | 2009-12-24 | 2011-07-07 | Panasonic Corp | フリップフロップ回路及び分周回路 |
| CN101841901B (zh) * | 2009-12-30 | 2013-01-02 | 中国科学院电子学研究所 | 射频信道闭环自动增益控制装置及方法 |
| JP2012165606A (ja) * | 2011-02-09 | 2012-08-30 | Handotai Rikougaku Kenkyu Center:Kk | 電源装置 |
| JP5724775B2 (ja) * | 2011-09-12 | 2015-05-27 | ソニー株式会社 | 集積回路 |
| US8633753B2 (en) * | 2012-02-09 | 2014-01-21 | Analog Devices, Inc. | Clock distribution system and method for a multi-bit latch |
| JP2014140100A (ja) * | 2013-01-21 | 2014-07-31 | Sony Corp | 位相比較回路及びデータ受信装置 |
| KR101965375B1 (ko) | 2013-03-15 | 2019-04-03 | 퀄컴 인코포레이티드 | 저 전력 아키텍처들 |
-
2014
- 2014-03-14 KR KR1020157027799A patent/KR101965375B1/ko active Active
- 2014-03-14 HU HUE14723581A patent/HUE042764T2/hu unknown
- 2014-03-14 JP JP2016503205A patent/JP6262330B2/ja active Active
- 2014-03-14 ES ES14723581T patent/ES2706477T3/es active Active
- 2014-03-14 CN CN201480013290.1A patent/CN105144579B/zh active Active
- 2014-03-14 WO PCT/US2014/029721 patent/WO2014145066A2/en not_active Ceased
- 2014-03-14 EP EP14723581.6A patent/EP2974018B1/en active Active
- 2014-03-14 KR KR1020197008612A patent/KR101970612B1/ko active Active
- 2014-03-14 CN CN201710515078.0A patent/CN107302350B/zh active Active
- 2014-03-14 US US14/213,907 patent/US9184733B2/en active Active
-
2015
- 2015-09-18 US US14/858,966 patent/US9595944B2/en active Active
-
2017
- 2017-12-13 JP JP2017238415A patent/JP6517312B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP2974018A2 (en) | 2016-01-20 |
| CN107302350A (zh) | 2017-10-27 |
| KR20190033665A (ko) | 2019-03-29 |
| CN105144579B (zh) | 2018-06-01 |
| CN105144579A (zh) | 2015-12-09 |
| US9595944B2 (en) | 2017-03-14 |
| KR20150129789A (ko) | 2015-11-20 |
| US20140266369A1 (en) | 2014-09-18 |
| KR101965375B1 (ko) | 2019-04-03 |
| WO2014145066A2 (en) | 2014-09-18 |
| HUE042764T2 (hu) | 2019-07-29 |
| JP6262330B2 (ja) | 2018-01-17 |
| JP2016521400A (ja) | 2016-07-21 |
| JP2018077871A (ja) | 2018-05-17 |
| EP2974018B1 (en) | 2018-11-21 |
| KR101970612B1 (ko) | 2019-08-13 |
| US9184733B2 (en) | 2015-11-10 |
| WO2014145066A3 (en) | 2014-11-06 |
| CN107302350B (zh) | 2020-11-27 |
| US20160013775A1 (en) | 2016-01-14 |
| JP6517312B2 (ja) | 2019-05-22 |
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