KR101710862B1 - 인쇄된 전자장치를 위한 인쇄-적합 디자인 및 레이아웃 - Google Patents

인쇄된 전자장치를 위한 인쇄-적합 디자인 및 레이아웃 Download PDF

Info

Publication number
KR101710862B1
KR101710862B1 KR1020127002943A KR20127002943A KR101710862B1 KR 101710862 B1 KR101710862 B1 KR 101710862B1 KR 1020127002943 A KR1020127002943 A KR 1020127002943A KR 20127002943 A KR20127002943 A KR 20127002943A KR 101710862 B1 KR101710862 B1 KR 101710862B1
Authority
KR
South Korea
Prior art keywords
structures
width
minimum
length
features
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020127002943A
Other languages
English (en)
Korean (ko)
Other versions
KR20120052273A (ko
Inventor
치강 왕
비벡 서브라마니안
리 클리버랜드
Original Assignee
씬 필름 일렉트로닉스 에이에스에이
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 씬 필름 일렉트로닉스 에이에스에이 filed Critical 씬 필름 일렉트로닉스 에이에스에이
Publication of KR20120052273A publication Critical patent/KR20120052273A/ko
Application granted granted Critical
Publication of KR101710862B1 publication Critical patent/KR101710862B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0085—Apparatus for treatments of printed circuits with liquids not provided for in groups H05K3/02 - H05K3/46; conveyors and holding means therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/5328—Conductive materials containing conductive organic materials or pastes, e.g. conductive adhesives, inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • H10K71/611—Forming conductive regions or layers, e.g. electrodes using printing deposition, e.g. ink jet printing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09245—Crossing layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1241—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing
    • H05K3/125—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing by ink-jet printing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structure Of Printed Boards (AREA)
KR1020127002943A 2009-08-05 2010-08-05 인쇄된 전자장치를 위한 인쇄-적합 디자인 및 레이아웃 Active KR101710862B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US23164309P 2009-08-05 2009-08-05
US61/231,643 2009-08-05
US25580409P 2009-10-28 2009-10-28
US61/255,804 2009-10-28
PCT/US2010/044598 WO2011017552A1 (en) 2009-08-05 2010-08-05 Print compatible designs and layout schemes for printed electronics

Publications (2)

Publication Number Publication Date
KR20120052273A KR20120052273A (ko) 2012-05-23
KR101710862B1 true KR101710862B1 (ko) 2017-02-28

Family

ID=43544671

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020127002943A Active KR101710862B1 (ko) 2009-08-05 2010-08-05 인쇄된 전자장치를 위한 인쇄-적합 디자인 및 레이아웃

Country Status (6)

Country Link
US (2) US8383952B2 (enExample)
JP (1) JP2013501383A (enExample)
KR (1) KR101710862B1 (enExample)
CN (1) CN102474254A (enExample)
TW (1) TWI573496B (enExample)
WO (1) WO2011017552A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT12741U1 (de) * 2011-03-10 2012-10-15 Forster Verkehrs Und Werbetechnik Gmbh Anordnung mit elektrischen/elektronischen bauteilen
WO2015075310A1 (en) * 2013-11-19 2015-05-28 Teknologian Tutkimuskeskus Vtt Oy A method for the fabrication and use of electronic circuits and an electronics circuit structure
GB2543528B (en) * 2015-10-20 2020-01-15 Advanced Risc Mach Ltd Memory circuit
WO2019036304A1 (en) * 2017-08-18 2019-02-21 Thin Film Electronics Asa SPRAY-COATED DETECTION LINES, SAFETY AND / OR IDENTIFICATION LABELS AND DEVICES COMPRISING THE SAME, AND METHODS OF MAKING
US20210189165A1 (en) * 2017-10-19 2021-06-24 Hewlett-Packard Development Company, L.P. Printable ammonium-based chalcogenometalate fluids
US10306749B1 (en) * 2018-02-19 2019-05-28 Dell Products L.P. System and method of utilizing serpentine regions
CN113486621B (zh) * 2021-06-28 2024-03-01 深圳市华星光电半导体显示技术有限公司 像素电路的设计方法、装置、控制器及存储介质

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5811750B2 (ja) * 1979-06-04 1983-03-04 株式会社日立製作所 高耐圧抵抗素子
JPS607147A (ja) * 1983-06-24 1985-01-14 Mitsubishi Electric Corp 半導体装置
US4685203A (en) * 1983-09-13 1987-08-11 Mitsubishi Denki Kabushiki Kaisha Hybrid integrated circuit substrate and method of manufacturing the same
JPH02163960A (ja) * 1988-12-16 1990-06-25 Toshiba Corp 半導体装置
JPH0750710B2 (ja) * 1990-06-06 1995-05-31 富士ゼロックス株式会社 多層配線構造
FR2702595B1 (fr) * 1993-03-11 1996-05-24 Toshiba Kk Structure de câblage multicouche.
US5764488A (en) * 1996-06-11 1998-06-09 Ast Research, Inc. Printed circuit board having a dual pattern footprint for receiving one of two component packages
US5805428A (en) * 1996-12-20 1998-09-08 Compaq Computer Corporation Transistor/resistor printed circuit board layout
EP0909117B1 (en) * 1997-10-08 2006-01-04 Delphi Technologies, Inc. Method of making thick film circuits
JP3070678B2 (ja) * 1998-03-24 2000-07-31 日本電気株式会社 図形レイアウト変更システム及び図形レイアウト変更方法
JP4228418B2 (ja) * 1998-07-30 2009-02-25 沖電気工業株式会社 半導体装置
US6691297B1 (en) * 1999-03-04 2004-02-10 Matsushita Electric Industrial Co., Ltd. Method for planning layout for LSI pattern, method for forming LSI pattern and method for generating mask data for LSI
US6238824B1 (en) * 1999-08-31 2001-05-29 Micron Technology, Inc. Method for designing and making photolithographic reticle, reticle, and photolithographic process
TW438198U (en) * 1999-10-14 2001-05-28 Via Tech Inc Wiring structure of a printed circuit board
US6574711B2 (en) * 1999-12-27 2003-06-03 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit
US6792590B1 (en) * 2000-09-29 2004-09-14 Numerical Technologies, Inc. Dissection of edges with projection points in a fabrication layout for correcting proximity effects
DE10059498A1 (de) * 2000-11-30 2002-06-13 Infineon Technologies Ag Substrat mit einer halbleitenden Schicht, elektronisches Bauelement mit diesem Substrat, elektronische Schaltung mit mindestens einem solchen elektronischen Bauelement, druckbare Zusammensetzung sowie Verfahren zur Herstellung eines Substrats
US6858928B1 (en) * 2000-12-07 2005-02-22 Cadence Design Systems, Inc. Multi-directional wiring on a single metal layer
US6664639B2 (en) * 2000-12-22 2003-12-16 Matrix Semiconductor, Inc. Contact and via structure and method of fabrication
US6492736B1 (en) * 2001-03-14 2002-12-10 Lsi Logic Corporation Power mesh bridge
JP2002312414A (ja) * 2001-04-13 2002-10-25 Toshiba Corp 半導体集積回路装置のレイアウト設計システム、配線設計方法、配線設計プログラム及び半導体集積回路装置の製造方法
TW522764B (en) * 2001-08-28 2003-03-01 Via Tech Inc Power layout structure on host bridge chip substrate and motherboard
US6825509B1 (en) * 2001-11-26 2004-11-30 Corrent Corporation Power distribution system, method, and layout for an electronic device
US7739624B2 (en) * 2002-07-29 2010-06-15 Synopsys, Inc. Methods and apparatuses to generate a shielding mesh for integrated circuit devices
GB0225202D0 (en) * 2002-10-30 2002-12-11 Hewlett Packard Co Electronic components
US6874133B2 (en) 2002-12-04 2005-03-29 Cadence Design Systems, Inc. Integrated circuit design layout compaction method
JP2004335887A (ja) * 2003-05-09 2004-11-25 Canon Inc プリント配線基板及び該基板を用いた装置
US7124390B2 (en) 2003-07-25 2006-10-17 Mentor Graphics Corporation Generating a split power plane of a multi-layer printed circuit board
TW591985B (en) * 2003-10-15 2004-06-11 Benq Corp PCB having a circuit layout for preventing the PCB from bending when heated
JP2007536581A (ja) * 2004-05-07 2007-12-13 メンター・グラフィクス・コーポレーション プロセス変動バンドを用いた集積回路レイアウト設計法
US7161823B2 (en) * 2004-06-03 2007-01-09 Samsung Electronics Co., Ltd. Semiconductor memory device and method of arranging signal and power lines thereof
TWI259043B (en) * 2004-11-19 2006-07-21 Realtek Semiconductor Corp Structure of circuit layout and method thereof
WO2006076606A2 (en) * 2005-01-14 2006-07-20 Cabot Corporation Optimized multi-layer printing of electronics and displays
JP2006253498A (ja) * 2005-03-11 2006-09-21 Matsushita Electric Ind Co Ltd 半導体集積回路装置
US7446352B2 (en) * 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
JP5050413B2 (ja) * 2006-06-09 2012-10-17 富士通株式会社 設計支援プログラム、該プログラムを記録した記録媒体、設計支援方法、および設計支援装置
US7624500B2 (en) * 2006-08-16 2009-12-01 Lexmark International, Inc. Printing of multi-layer circuits
US7615706B2 (en) * 2006-08-21 2009-11-10 Tpo Displays Corp. Layout of a printed circuit board
US20080072204A1 (en) * 2006-09-19 2008-03-20 Inventec Corporation Layout design of multilayer printed circuit board
US7493436B2 (en) * 2006-10-26 2009-02-17 International Business Machines Corporation Interrupt handling using simultaneous multi-threading
US7892872B2 (en) * 2007-01-03 2011-02-22 Nanogram Corporation Silicon/germanium oxide particle inks, inkjet printing and processes for doping semiconductor substrates
JP5521270B2 (ja) * 2007-02-21 2014-06-11 凸版印刷株式会社 薄膜トランジスタアレイ、薄膜トランジスタアレイの製造方法、および薄膜トランジスタアレイを用いたアクティブマトリクス型ディスプレイ
US7979983B2 (en) 2007-04-04 2011-07-19 Cisco Technology, Inc. Connection an integrated circuit on a surface layer of a printed circuit board
TWI363210B (en) * 2007-04-04 2012-05-01 Au Optronics Corp Layout structure for chip coupling
TWI370464B (en) * 2007-04-19 2012-08-11 Ind Tech Res Inst Resistance layout structure and manufacture method thereof
US8453094B2 (en) * 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect

Also Published As

Publication number Publication date
JP2013501383A (ja) 2013-01-10
WO2011017552A1 (en) 2011-02-10
CN102474254A (zh) 2012-05-23
KR20120052273A (ko) 2012-05-23
TW201125445A (en) 2011-07-16
US9155202B2 (en) 2015-10-06
TWI573496B (zh) 2017-03-01
US20110186333A1 (en) 2011-08-04
US20130146334A1 (en) 2013-06-13
US8383952B2 (en) 2013-02-26

Similar Documents

Publication Publication Date Title
KR101710862B1 (ko) 인쇄된 전자장치를 위한 인쇄-적합 디자인 및 레이아웃
JP5692924B2 (ja) プリント不揮発性メモリ
US8530589B2 (en) Print processing for patterned conductor, semiconductor and dielectric materials
US8796125B2 (en) Printed, self-aligned, top gate thin film transistor
KR20160040319A (ko) 전기 활성 디바이스 및 그 제조 방법
US8748242B2 (en) Electronic circuit structure and method for forming same
JP2011511441A (ja) シリコン薄膜トランジスタ、並びにその製造システム及び方法
CN102770948A (zh) 制造包括凹型的晶体管的方法
TW200845398A (en) Semiconductor device and manufacture method thereof
TW201921498A (zh) 選擇性氧化鋁蝕刻的使用
JP2017139276A (ja) 半導体装置
KR20140082681A (ko) 반도체 디바이스 제조를 위한 프로세스
WO2009075739A2 (en) Forming thin film transistors using ablative films
US20090278134A1 (en) Semiconductor device and method of manufacturing the semiconductor device
US9123815B1 (en) VTFTs including offset electrodes
TW201320346A (zh) 具有減小寄生電容之垂直電晶體
CN1951162B (zh) 元件配置基板及其制备方法
US7537883B2 (en) Method of manufacturing nano size-gap electrode device
WO2015134092A1 (en) Vtft including overlapping electrodes
JP2005038895A (ja) トランジスタの製造方法、電気光学装置、電子機器
JP2005209696A (ja) 半導体装置の製造方法
CN108321122B (zh) Cmos薄膜晶体管及其制备方法和显示装置
US9142647B1 (en) VTFT formation using selective area deposition
CN100562978C (zh) 印刷式自对准上闸极薄膜晶体管
JP4617642B2 (ja) 配線基板の製造方法、及び電気光学装置の製造方法

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20120202

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20150708

Comment text: Request for Examination of Application

N231 Notification of change of applicant
PN2301 Change of applicant

Patent event date: 20150824

Comment text: Notification of Change of Applicant

Patent event code: PN23011R01D

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20160528

Patent event code: PE09021S01D

PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20161130

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20170222

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20170222

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20191223

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20210204

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20220207

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20240207

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20250217

Start annual number: 9

End annual number: 9