KR101615789B1 - 반도체 소자용 기판의 제조 방법 및 반도체 장치 - Google Patents

반도체 소자용 기판의 제조 방법 및 반도체 장치 Download PDF

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KR101615789B1
KR101615789B1 KR1020117022639A KR20117022639A KR101615789B1 KR 101615789 B1 KR101615789 B1 KR 101615789B1 KR 1020117022639 A KR1020117022639 A KR 1020117022639A KR 20117022639 A KR20117022639 A KR 20117022639A KR 101615789 B1 KR101615789 B1 KR 101615789B1
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South Korea
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substrate
forming
pattern
resin layer
resin
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KR1020117022639A
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English (en)
Korean (ko)
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KR20120004423A (ko
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스스무 마니와
다께히또 쯔까모또
준꼬 도다
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도판 인사츠 가부시키가이샤
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Publication of KR20120004423A publication Critical patent/KR20120004423A/ko
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861Lead-frames fixed on or encapsulated in insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020117022639A 2009-03-30 2010-03-15 반도체 소자용 기판의 제조 방법 및 반도체 장치 KR101615789B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009081785A JP5526575B2 (ja) 2009-03-30 2009-03-30 半導体素子用基板の製造方法および半導体装置
JPJP-P-2009-081785 2009-03-30

Publications (2)

Publication Number Publication Date
KR20120004423A KR20120004423A (ko) 2012-01-12
KR101615789B1 true KR101615789B1 (ko) 2016-04-26

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KR1020117022639A KR101615789B1 (ko) 2009-03-30 2010-03-15 반도체 소자용 기판의 제조 방법 및 반도체 장치

Country Status (7)

Country Link
US (1) US8535987B2 (ja)
JP (1) JP5526575B2 (ja)
KR (1) KR101615789B1 (ja)
CN (1) CN102365737B (ja)
SG (1) SG174622A1 (ja)
TW (1) TWI500131B (ja)
WO (1) WO2010116615A1 (ja)

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US8709933B2 (en) * 2011-04-21 2014-04-29 Tessera, Inc. Interposer having molded low CTE dielectric
WO2013052672A2 (en) * 2011-10-07 2013-04-11 Volterra Semiconductor Corporation Power management applications of interconnect substrates
JP6050975B2 (ja) * 2012-03-27 2016-12-21 新光電気工業株式会社 リードフレーム、半導体装置及びリードフレームの製造方法
CN102779763A (zh) * 2012-06-05 2012-11-14 华天科技(西安)有限公司 一种基于腐蚀的aaqfn产品的二次塑封制作工艺
CN102738017A (zh) * 2012-06-13 2012-10-17 华天科技(西安)有限公司 一种基于喷砂的aaqfn产品的二次塑封制作工艺
CN102738016A (zh) * 2012-06-13 2012-10-17 华天科技(西安)有限公司 一种基于框架载体开孔的aaqfn产品的二次塑封制作工艺
CN103021875A (zh) * 2012-12-09 2013-04-03 华天科技(西安)有限公司 一种基于aaqfn框架产品二次塑封的扁平封装件制作工艺
CN103021883A (zh) * 2012-12-09 2013-04-03 华天科技(西安)有限公司 一种基于腐蚀塑封体的扁平封装件制作工艺
CN103021882A (zh) * 2012-12-09 2013-04-03 华天科技(西安)有限公司 一种基于磨屑塑封体的扁平封装件制作工艺
CN103021994A (zh) * 2012-12-28 2013-04-03 华天科技(西安)有限公司 一种aaqfn二次塑封与二次植球优化的封装件及其制作工艺
CN104359393B (zh) * 2014-11-28 2018-08-24 中航电测仪器股份有限公司 一种应变计及其制造和安装方法
JP2018019071A (ja) 2016-07-14 2018-02-01 住友ベークライト株式会社 半導体装置の製造方法
JP6964477B2 (ja) 2017-09-20 2021-11-10 新光電気工業株式会社 半導体素子用基板及びその製造方法、半導体装置及びその製造方法
KR101999594B1 (ko) * 2018-02-23 2019-10-01 해성디에스 주식회사 반도체 패키지 기판 제조방법, 이를 이용하여 제조된 반도체 패키지 기판, 반도체 패키지 제조방법 및 이를 이용하여 제조된 반도체 패키지
KR102119142B1 (ko) 2019-10-01 2020-06-05 해성디에스 주식회사 웨이퍼 레벨 패키지의 캐리어를 리드 프레임으로 제작하는 방법
US11441697B2 (en) 2020-10-01 2022-09-13 Saudi Arabian Oil Company Valve diagnostic and performance system
US11692903B2 (en) 2020-10-01 2023-07-04 Saudi Arabian Oil Company Valve diagnostic and performance system
US11581251B2 (en) 2020-11-10 2023-02-14 Qualcomm Incorporated Package comprising inter-substrate gradient interconnect structure

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JPH09307043A (ja) * 1996-05-10 1997-11-28 Dainippon Printing Co Ltd リードフレーム部材とその製造方法、および該リードフレーム部材を用いた半導体装置
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JP4609172B2 (ja) 2005-04-21 2011-01-12 株式会社デンソー 樹脂封止型半導体装置

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Publication number Priority date Publication date Assignee Title
JP2003309242A (ja) * 2002-04-15 2003-10-31 Dainippon Printing Co Ltd リードフレーム部材とリードフレーム部材の製造方法、及び該リードフレーム部材を用いた半導体パッケージとその製造方法

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US20120061829A1 (en) 2012-03-15
JP5526575B2 (ja) 2014-06-18
US8535987B2 (en) 2013-09-17
JP2010238694A (ja) 2010-10-21
TWI500131B (zh) 2015-09-11
WO2010116615A1 (ja) 2010-10-14
SG174622A1 (en) 2011-10-28
KR20120004423A (ko) 2012-01-12
CN102365737A (zh) 2012-02-29
CN102365737B (zh) 2014-04-02
TW201044532A (en) 2010-12-16

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