KR101499486B1 - 반도체 기판의 제작 방법 및 반도체 장치의 제작 방법 - Google Patents

반도체 기판의 제작 방법 및 반도체 장치의 제작 방법 Download PDF

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Publication number
KR101499486B1
KR101499486B1 KR1020080107639A KR20080107639A KR101499486B1 KR 101499486 B1 KR101499486 B1 KR 101499486B1 KR 1020080107639 A KR1020080107639 A KR 1020080107639A KR 20080107639 A KR20080107639 A KR 20080107639A KR 101499486 B1 KR101499486 B1 KR 101499486B1
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single crystal
semiconductor substrate
crystal semiconductor
ions
layer
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KR20090045116A (ko
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순페이 야마자키
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가부시키가이샤 한도오따이 에네루기 켄큐쇼
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1020080107639A 2007-11-01 2008-10-31 반도체 기판의 제작 방법 및 반도체 장치의 제작 방법 Expired - Fee Related KR101499486B1 (ko)

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JPJP-P-2007-285504 2007-11-01
JP2007285504 2007-11-01

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KR20090045116A KR20090045116A (ko) 2009-05-07
KR101499486B1 true KR101499486B1 (ko) 2015-03-06

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KR1020080107639A Expired - Fee Related KR101499486B1 (ko) 2007-11-01 2008-10-31 반도체 기판의 제작 방법 및 반도체 장치의 제작 방법

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US (1) US8163628B2 (https=)
JP (1) JP5634020B2 (https=)
KR (1) KR101499486B1 (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010114431A (ja) * 2008-10-10 2010-05-20 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
JP2011029610A (ja) * 2009-06-26 2011-02-10 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
US8513090B2 (en) * 2009-07-16 2013-08-20 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate, and semiconductor device
JP6076584B2 (ja) * 2011-02-02 2017-02-08 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
JP5977617B2 (ja) * 2012-08-08 2016-08-24 東京エレクトロン株式会社 被処理体のマイクロ波処理方法及びマイクロ波処理装置
JP6056516B2 (ja) * 2013-02-01 2017-01-11 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ
KR102462742B1 (ko) 2013-12-02 2022-11-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치 및 그 제조방법
KR20160137129A (ko) * 2015-05-22 2016-11-30 엘지디스플레이 주식회사 박막트랜지스터, 그를 포함하는 표시 장치 및 그 박막트랜지스터의 제조 방법
FR3061988B1 (fr) * 2017-01-13 2019-11-01 Soitec Procede de lissage de surface d'un substrat semiconducteur sur isolant
JP7125104B2 (ja) * 2018-07-02 2022-08-24 株式会社Joled 表示パネル製造装置
US12041842B2 (en) 2018-07-02 2024-07-16 Jdi Design And Development G.K. Display panel patterning device
US10553474B1 (en) * 2018-08-29 2020-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a semiconductor-on-insulator (SOI) substrate
KR20210070417A (ko) * 2019-12-04 2021-06-15 삼성디스플레이 주식회사 표시 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
JP2000077287A (ja) * 1998-08-26 2000-03-14 Nissin Electric Co Ltd 結晶薄膜基板の製造方法
JP2002170942A (ja) * 2000-11-30 2002-06-14 Seiko Epson Corp Ｓｏｉ基板、素子基板、電気光学装置及び電子機器、並びにｓｏｉ基板の製造方法、素子基板の製造方法
JP2002280531A (ja) * 2001-03-19 2002-09-27 Denso Corp 半導体基板及びその製造方法

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4529571A (en) 1982-10-27 1985-07-16 The United States Of America As Represented By The United States Department Of Energy Single-ring magnetic cusp low gas pressure ion source
JPH0834198B2 (ja) * 1990-11-28 1996-03-29 信越半導体株式会社 Ｓｏｉ基板における単結晶薄膜層の膜厚制御方法
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP4103968B2 (ja) 1996-09-18 2008-06-18 株式会社半導体エネルギー研究所 絶縁ゲイト型半導体装置
US6103599A (en) * 1997-07-25 2000-08-15 Silicon Genesis Corporation Planarizing technique for multilayered substrates
US6388652B1 (en) 1997-08-20 2002-05-14 Semiconductor Energy Laboratory Co., Ltd. Electrooptical device
US6686623B2 (en) 1997-11-18 2004-02-03 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile memory and electronic apparatus
JP3697106B2 (ja) * 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
JP2000012864A (ja) 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US6271101B1 (en) 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
JP4476390B2 (ja) * 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP2000349266A (ja) 1999-03-26 2000-12-15 Canon Inc 半導体部材の製造方法、半導体基体の利用方法、半導体部材の製造システム、半導体部材の生産管理方法及び堆積膜形成装置の利用方法
JP2002033399A (ja) 2000-07-13 2002-01-31 Toshiba Corp 半導体集積回路及びその製造方法
US6566158B2 (en) 2001-08-17 2003-05-20 Rosemount Aerospace Inc. Method of preparing a semiconductor using ion implantation in a SiC layer
JP2004362901A (ja) 2003-06-04 2004-12-24 Sharp Corp イオンドーピング装置、イオンドーピング方法および半導体装置
JP4759919B2 (ja) * 2004-01-16 2011-08-31 セイコーエプソン株式会社 電気光学装置の製造方法
JP5110772B2 (ja) * 2004-02-03 2012-12-26 株式会社半導体エネルギー研究所 半導体薄膜層を有する基板の製造方法
US7148124B1 (en) 2004-11-18 2006-12-12 Alexander Yuri Usenko Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers
KR20080042095A (ko) * 2005-07-27 2008-05-14 실리콘 제너시스 코포레이션 제어된 클리빙 처리를 이용하여 플레이트 상에 다수의 타일영역을 제작하는 방법 및 구조
US20070281440A1 (en) * 2006-05-31 2007-12-06 Jeffrey Scott Cites Producing SOI structure using ion shower
US8153513B2 (en) 2006-07-25 2012-04-10 Silicon Genesis Corporation Method and system for continuous large-area scanning implantation process
CN101281912B (zh) 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
KR101400699B1 (ko) 2007-05-18 2014-05-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 기판 및 반도체 장치 및 그 제조 방법
JP5459899B2 (ja) 2007-06-01 2014-04-02 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7781306B2 (en) 2007-06-20 2010-08-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor substrate and method for manufacturing the same
US20090004764A1 (en) 2007-06-29 2009-01-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing semiconductor device
EP2009687B1 (en) 2007-06-29 2016-08-17 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing an SOI substrate and method of manufacturing a semiconductor device
US7678668B2 (en) 2007-07-04 2010-03-16 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device
JP5325404B2 (ja) 2007-09-21 2013-10-23 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
JP2000077287A (ja) * 1998-08-26 2000-03-14 Nissin Electric Co Ltd 結晶薄膜基板の製造方法
JP2002170942A (ja) * 2000-11-30 2002-06-14 Seiko Epson Corp Ｓｏｉ基板、素子基板、電気光学装置及び電子機器、並びにｓｏｉ基板の製造方法、素子基板の製造方法
JP2002280531A (ja) * 2001-03-19 2002-09-27 Denso Corp 半導体基板及びその製造方法

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Publication number Publication date
KR20090045116A (ko) 2009-05-07
US8163628B2 (en) 2012-04-24
JP5634020B2 (ja) 2014-12-03
US20090117703A1 (en) 2009-05-07
JP2009135469A (ja) 2009-06-18

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