KR101455251B1 - 기판 처리 방법과 반도체 장치의 제조 방법 및 기판 처리 장치 - Google Patents
기판 처리 방법과 반도체 장치의 제조 방법 및 기판 처리 장치 Download PDFInfo
- Publication number
- KR101455251B1 KR101455251B1 KR1020130060848A KR20130060848A KR101455251B1 KR 101455251 B1 KR101455251 B1 KR 101455251B1 KR 1020130060848 A KR1020130060848 A KR 1020130060848A KR 20130060848 A KR20130060848 A KR 20130060848A KR 101455251 B1 KR101455251 B1 KR 101455251B1
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- South Korea
- Prior art keywords
- doped silicon
- substrate
- silicon
- single crystal
- amorphous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02529—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
- H01L21/67757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber vertical transfer of a batch of workpieces
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
- H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Vapour Deposition (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012131857A JP2013258188A (ja) | 2012-06-11 | 2012-06-11 | 基板処理方法と半導体装置の製造方法、および基板処理装置 |
| JPJP-P-2012-131857 | 2012-06-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20130138674A KR20130138674A (ko) | 2013-12-19 |
| KR101455251B1 true KR101455251B1 (ko) | 2014-10-27 |
Family
ID=49774780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020130060848A Active KR101455251B1 (ko) | 2012-06-11 | 2013-05-29 | 기판 처리 방법과 반도체 장치의 제조 방법 및 기판 처리 장치 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20130344689A1 (enExample) |
| JP (1) | JP2013258188A (enExample) |
| KR (1) | KR101455251B1 (enExample) |
| TW (1) | TWI497610B (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6338904B2 (ja) * | 2014-03-24 | 2018-06-06 | 株式会社Screenホールディングス | 基板処理装置 |
| JP6560991B2 (ja) * | 2016-01-29 | 2019-08-14 | 株式会社Kokusai Electric | 半導体装置の製造方法、基板処理装置およびプログラム |
| JP7199286B2 (ja) * | 2019-03-29 | 2023-01-05 | 東京エレクトロン株式会社 | 基板処理装置 |
| US11302836B2 (en) * | 2020-01-14 | 2022-04-12 | Hoon Kim | Plasmonic field-enhanced photodetector and image sensor using light absorbing layer having split conduction band and valence band |
| KR102824349B1 (ko) * | 2022-04-28 | 2025-06-23 | 가부시키가이샤 코쿠사이 엘렉트릭 | 기판 처리 방법, 반도체 장치의 제조 방법, 프로그램 및 기판 처리 장치 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11288883A (ja) * | 1998-02-25 | 1999-10-19 | Siemens Ag | 多結晶シリコン構造体に対する製造方法 |
| KR20000070658A (ko) * | 1997-01-31 | 2000-11-25 | 마클 데이빗 에이. | 소형 집적회로의 제조방법 |
| JP2001291850A (ja) * | 2000-04-10 | 2001-10-19 | Hitachi Cable Ltd | 結晶シリコン薄膜の製造方法 |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6158879A (ja) * | 1984-08-29 | 1986-03-26 | Nec Corp | シリコン薄膜結晶の製造方法 |
| JPH05226657A (ja) * | 1992-02-10 | 1993-09-03 | Nippondenso Co Ltd | 薄膜トランジスタおよびその製造方法 |
| JP3009979B2 (ja) * | 1993-07-05 | 2000-02-14 | シャープ株式会社 | 半導体装置及びその製造方法 |
| JPH0982651A (ja) * | 1995-09-14 | 1997-03-28 | Toshiba Corp | 半導体装置の製造方法 |
| TW328650B (en) * | 1996-08-27 | 1998-03-21 | United Microelectronics Corp | The MOS device and its manufacturing method |
| JPH10326837A (ja) * | 1997-03-25 | 1998-12-08 | Toshiba Corp | 半導体集積回路装置の製造方法、半導体集積回路装置、半導体装置、及び、半導体装置の製造方法 |
| US6346732B1 (en) * | 1999-05-14 | 2002-02-12 | Kabushiki Kaisha Toshiba | Semiconductor device with oxide mediated epitaxial layer |
| JP3886085B2 (ja) * | 1999-05-14 | 2007-02-28 | 株式会社東芝 | 半導体エピタキシャル基板の製造方法 |
| JP3492973B2 (ja) * | 2000-03-30 | 2004-02-03 | 株式会社東芝 | 半導体装置の製造方法 |
| EP1287555A1 (en) * | 2000-05-31 | 2003-03-05 | Infineon Technologies North America Corp. | Process for forming doped epitaxial silicon on a silicon substrate |
| EP1296361A1 (en) * | 2001-09-13 | 2003-03-26 | STMicroelectronics S.r.l. | A process of forming an interface free layer of silicon on a substrate of monocrystalline silicon |
| KR100680946B1 (ko) * | 2004-04-28 | 2007-02-08 | 주식회사 하이닉스반도체 | 반도체 소자의 콘택 플러그 형성방법 |
| US7361563B2 (en) * | 2004-06-17 | 2008-04-22 | Samsung Electronics Co., Ltd. | Methods of fabricating a semiconductor device using a selective epitaxial growth technique |
| JP2007329200A (ja) * | 2006-06-06 | 2007-12-20 | Toshiba Corp | 半導体装置の製造方法 |
| US7776698B2 (en) * | 2007-10-05 | 2010-08-17 | Applied Materials, Inc. | Selective formation of silicon carbon epitaxial layer |
| JP5023004B2 (ja) * | 2008-06-30 | 2012-09-12 | 株式会社日立国際電気 | 基板処理方法及び基板処理装置 |
| JP2010141079A (ja) * | 2008-12-11 | 2010-06-24 | Hitachi Kokusai Electric Inc | 半導体装置の製造方法 |
| US8313999B2 (en) * | 2009-12-23 | 2012-11-20 | Intel Corporation | Multi-gate semiconductor device with self-aligned epitaxial source and drain |
-
2012
- 2012-06-11 JP JP2012131857A patent/JP2013258188A/ja active Pending
-
2013
- 2013-05-29 KR KR1020130060848A patent/KR101455251B1/ko active Active
- 2013-06-10 TW TW102120506A patent/TWI497610B/zh active
- 2013-06-11 US US13/915,054 patent/US20130344689A1/en not_active Abandoned
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000070658A (ko) * | 1997-01-31 | 2000-11-25 | 마클 데이빗 에이. | 소형 집적회로의 제조방법 |
| JPH11288883A (ja) * | 1998-02-25 | 1999-10-19 | Siemens Ag | 多結晶シリコン構造体に対する製造方法 |
| JP2001291850A (ja) * | 2000-04-10 | 2001-10-19 | Hitachi Cable Ltd | 結晶シリコン薄膜の製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2013258188A (ja) | 2013-12-26 |
| KR20130138674A (ko) | 2013-12-19 |
| TWI497610B (zh) | 2015-08-21 |
| US20130344689A1 (en) | 2013-12-26 |
| TW201405669A (zh) | 2014-02-01 |
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