TWI497610B - Semiconductor device manufacturing method and substrate processing device - Google Patents

Semiconductor device manufacturing method and substrate processing device Download PDF

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Publication number
TWI497610B
TWI497610B TW102120506A TW102120506A TWI497610B TW I497610 B TWI497610 B TW I497610B TW 102120506 A TW102120506 A TW 102120506A TW 102120506 A TW102120506 A TW 102120506A TW I497610 B TWI497610 B TW I497610B
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TW
Taiwan
Prior art keywords
gas
doped
film
substrate
phosphorus
Prior art date
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TW102120506A
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English (en)
Chinese (zh)
Other versions
TW201405669A (zh
Inventor
森谷敦
石橋清久
富成達也
Original Assignee
日立國際電氣股份有限公司
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Application filed by 日立國際電氣股份有限公司 filed Critical 日立國際電氣股份有限公司
Publication of TW201405669A publication Critical patent/TW201405669A/zh
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Publication of TWI497610B publication Critical patent/TWI497610B/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3408—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3438—Doping during depositing
    • H10P14/3441—Conductivity type
    • H10P14/3442—N-type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/30—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for conveying, e.g. between different workstations
    • H10P72/33—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for conveying, e.g. between different workstations into and out of processing chamber
    • H10P72/3312—Vertical transfer of a batch of workpieces
TW102120506A 2012-06-11 2013-06-10 Semiconductor device manufacturing method and substrate processing device TWI497610B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012131857A JP2013258188A (ja) 2012-06-11 2012-06-11 基板処理方法と半導体装置の製造方法、および基板処理装置

Publications (2)

Publication Number Publication Date
TW201405669A TW201405669A (zh) 2014-02-01
TWI497610B true TWI497610B (zh) 2015-08-21

Family

ID=49774780

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102120506A TWI497610B (zh) 2012-06-11 2013-06-10 Semiconductor device manufacturing method and substrate processing device

Country Status (4)

Country Link
US (1) US20130344689A1 (enExample)
JP (1) JP2013258188A (enExample)
KR (1) KR101455251B1 (enExample)
TW (1) TWI497610B (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6338904B2 (ja) 2014-03-24 2018-06-06 株式会社Screenホールディングス 基板処理装置
JP6560991B2 (ja) * 2016-01-29 2019-08-14 株式会社Kokusai Electric 半導体装置の製造方法、基板処理装置およびプログラム
JP7199286B2 (ja) * 2019-03-29 2023-01-05 東京エレクトロン株式会社 基板処理装置
US11302836B2 (en) * 2020-01-14 2022-04-12 Hoon Kim Plasmonic field-enhanced photodetector and image sensor using light absorbing layer having split conduction band and valence band
TWI869793B (zh) * 2022-04-28 2025-01-11 日商國際電氣股份有限公司 基板處理方法、半導體裝置的製造方法、程式及基板處理裝置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6051509A (en) * 1997-03-25 2000-04-18 Kabushiki Kaisha Toshiba Semiconductor integrated circuit manufacturing method and device
US20030060028A1 (en) * 2001-09-13 2003-03-27 Stmicroelectronics S.R.L. Method for forming an interface free layer of silicon on a substrate of monocrystalline silicon
US20090325366A1 (en) * 2008-06-30 2009-12-31 Hitachi-Kokusai Electric Inc. Substrate processing method and substrate processing apparatus

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JPS6158879A (ja) * 1984-08-29 1986-03-26 Nec Corp シリコン薄膜結晶の製造方法
JPH05226657A (ja) * 1992-02-10 1993-09-03 Nippondenso Co Ltd 薄膜トランジスタおよびその製造方法
JP3009979B2 (ja) * 1993-07-05 2000-02-14 シャープ株式会社 半導体装置及びその製造方法
JPH0982651A (ja) * 1995-09-14 1997-03-28 Toshiba Corp 半導体装置の製造方法
TW328650B (en) * 1996-08-27 1998-03-21 United Microelectronics Corp The MOS device and its manufacturing method
US5908307A (en) * 1997-01-31 1999-06-01 Ultratech Stepper, Inc. Fabrication method for reduced-dimension FET devices
US6068928A (en) * 1998-02-25 2000-05-30 Siemens Aktiengesellschaft Method for producing a polycrystalline silicon structure and polycrystalline silicon layer to be produced by the method
US6346732B1 (en) * 1999-05-14 2002-02-12 Kabushiki Kaisha Toshiba Semiconductor device with oxide mediated epitaxial layer
JP3886085B2 (ja) * 1999-05-14 2007-02-28 株式会社東芝 半導体エピタキシャル基板の製造方法
JP3492973B2 (ja) * 2000-03-30 2004-02-03 株式会社東芝 半導体装置の製造方法
JP2001291850A (ja) * 2000-04-10 2001-10-19 Hitachi Cable Ltd 結晶シリコン薄膜の製造方法
WO2001093326A1 (en) * 2000-05-31 2001-12-06 Infineon Technologies North America Corp. Process for forming doped epitaxial silicon on a silicon substrate
KR100680946B1 (ko) * 2004-04-28 2007-02-08 주식회사 하이닉스반도체 반도체 소자의 콘택 플러그 형성방법
US7361563B2 (en) * 2004-06-17 2008-04-22 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device using a selective epitaxial growth technique
JP2007329200A (ja) * 2006-06-06 2007-12-20 Toshiba Corp 半導体装置の製造方法
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JP2010141079A (ja) * 2008-12-11 2010-06-24 Hitachi Kokusai Electric Inc 半導体装置の製造方法
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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6051509A (en) * 1997-03-25 2000-04-18 Kabushiki Kaisha Toshiba Semiconductor integrated circuit manufacturing method and device
US20030060028A1 (en) * 2001-09-13 2003-03-27 Stmicroelectronics S.R.L. Method for forming an interface free layer of silicon on a substrate of monocrystalline silicon
US20090325366A1 (en) * 2008-06-30 2009-12-31 Hitachi-Kokusai Electric Inc. Substrate processing method and substrate processing apparatus

Also Published As

Publication number Publication date
KR20130138674A (ko) 2013-12-19
TW201405669A (zh) 2014-02-01
KR101455251B1 (ko) 2014-10-27
US20130344689A1 (en) 2013-12-26
JP2013258188A (ja) 2013-12-26

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