KR101221787B1 - 반도체 장치 - Google Patents

반도체 장치 Download PDF

Info

Publication number
KR101221787B1
KR101221787B1 KR1020060075050A KR20060075050A KR101221787B1 KR 101221787 B1 KR101221787 B1 KR 101221787B1 KR 1020060075050 A KR1020060075050 A KR 1020060075050A KR 20060075050 A KR20060075050 A KR 20060075050A KR 101221787 B1 KR101221787 B1 KR 101221787B1
Authority
KR
South Korea
Prior art keywords
output
memory cell
buffer circuit
circuit
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020060075050A
Other languages
English (en)
Korean (ko)
Other versions
KR20070024358A (ko
Inventor
아쯔시 미야니시
Original Assignee
르네사스 일렉트로닉스 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 르네사스 일렉트로닉스 가부시키가이샤 filed Critical 르네사스 일렉트로닉스 가부시키가이샤
Publication of KR20070024358A publication Critical patent/KR20070024358A/ko
Application granted granted Critical
Publication of KR101221787B1 publication Critical patent/KR101221787B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Memories (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
KR1020060075050A 2005-08-26 2006-08-09 반도체 장치 Expired - Fee Related KR101221787B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005246408A JP4749089B2 (ja) 2005-08-26 2005-08-26 半導体装置
JPJP-P-2005-00246408 2005-08-26

Publications (2)

Publication Number Publication Date
KR20070024358A KR20070024358A (ko) 2007-03-02
KR101221787B1 true KR101221787B1 (ko) 2013-01-11

Family

ID=37778692

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060075050A Expired - Fee Related KR101221787B1 (ko) 2005-08-26 2006-08-09 반도체 장치

Country Status (5)

Country Link
US (3) US20070047283A1 (enExample)
JP (1) JP4749089B2 (enExample)
KR (1) KR101221787B1 (enExample)
CN (1) CN1921000B (enExample)
TW (1) TWI421873B (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009238332A (ja) 2008-03-27 2009-10-15 Renesas Technology Corp 半導体記憶装置
US9472268B2 (en) * 2010-07-16 2016-10-18 Texas Instruments Incorporated SRAM with buffered-read bit cells and its testing
US8837250B2 (en) * 2010-07-20 2014-09-16 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for word line decoder layout
US10249361B2 (en) * 2014-01-14 2019-04-02 Nvidia Corporation SRAM write driver with improved drive strength
US9589611B2 (en) 2015-04-01 2017-03-07 Semiconductor Energy Laboratory Co., Ltd. Memory device, semiconductor device, and electronic device
US10854284B1 (en) 2016-12-06 2020-12-01 Gsi Technology, Inc. Computational memory cell and processing array device with ratioless write port
US10847212B1 (en) 2016-12-06 2020-11-24 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers
US10847213B1 (en) 2016-12-06 2020-11-24 Gsi Technology, Inc. Write data processing circuits and methods associated with computational memory cells
US10770133B1 (en) 2016-12-06 2020-09-08 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits
US10891076B1 (en) 2016-12-06 2021-01-12 Gsi Technology, Inc. Results processing circuits and methods associated with computational memory cells
US10998040B2 (en) 2016-12-06 2021-05-04 Gsi Technology, Inc. Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
US10777262B1 (en) 2016-12-06 2020-09-15 Gsi Technology, Inc. Read data processing circuits and methods associated memory cells
US10943648B1 (en) 2016-12-06 2021-03-09 Gsi Technology, Inc. Ultra low VDD memory cell with ratioless write port
US11227653B1 (en) 2016-12-06 2022-01-18 Gsi Technology, Inc. Storage array circuits and methods for computational memory cells
US10521229B2 (en) 2016-12-06 2019-12-31 Gsi Technology, Inc. Computational memory cell and processing array device using memory cells
US10860320B1 (en) 2016-12-06 2020-12-08 Gsi Technology, Inc. Orthogonal data transposition system and method during data transfers to/from a processing array
US11631465B2 (en) 2018-07-03 2023-04-18 Samsung Electronics Co., Ltd. Non-volatile memory device
CN110675907B (zh) * 2018-07-03 2024-08-23 三星电子株式会社 非易失性存储器装置和在其内部传输数据的方法
CN109885154B (zh) * 2019-02-28 2023-06-23 江西天漪半导体有限公司 一种带旁路通道的低功耗寄存器
US10958272B2 (en) 2019-06-18 2021-03-23 Gsi Technology, Inc. Computational memory cell and processing array device using complementary exclusive or memory cells
US10877731B1 (en) 2019-06-18 2020-12-29 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features
US10930341B1 (en) 2019-06-18 2021-02-23 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04205787A (ja) * 1990-11-29 1992-07-27 Seiko Epson Corp マルチポートメモリ
JPH04356793A (ja) * 1990-08-18 1992-12-10 Mitsubishi Electric Corp 半導体記憶装置
JPH06195962A (ja) * 1992-12-24 1994-07-15 Ricoh Co Ltd シリアル記憶装置
JPH1073641A (ja) 1996-08-30 1998-03-17 Mitsubishi Electric Corp テスト回路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0329185A (ja) * 1989-06-26 1991-02-07 Nec Corp デュアルポートメモリー装置
JPH0574198A (ja) 1991-09-13 1993-03-26 Sony Corp テスト回路を備えたメモリ装置
JP3664777B2 (ja) * 1995-08-18 2005-06-29 株式会社ルネサステクノロジ 半導体記憶装置
JP3226886B2 (ja) * 1999-01-29 2001-11-05 エヌイーシーマイクロシステム株式会社 半導体記憶装置とその制御方法
JP2001023400A (ja) 1999-07-07 2001-01-26 Hitachi Ltd 半導体装置およびその不良解析方法
JP3835220B2 (ja) * 2001-08-31 2006-10-18 セイコーエプソン株式会社 半導体記憶装置
JP2004253499A (ja) * 2003-02-19 2004-09-09 Hitachi Ltd 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04356793A (ja) * 1990-08-18 1992-12-10 Mitsubishi Electric Corp 半導体記憶装置
JPH04205787A (ja) * 1990-11-29 1992-07-27 Seiko Epson Corp マルチポートメモリ
JPH06195962A (ja) * 1992-12-24 1994-07-15 Ricoh Co Ltd シリアル記憶装置
JPH1073641A (ja) 1996-08-30 1998-03-17 Mitsubishi Electric Corp テスト回路

Also Published As

Publication number Publication date
US20090185431A1 (en) 2009-07-23
US7898896B2 (en) 2011-03-01
CN1921000A (zh) 2007-02-28
US20070047283A1 (en) 2007-03-01
KR20070024358A (ko) 2007-03-02
TW200710864A (en) 2007-03-16
JP2007059026A (ja) 2007-03-08
CN1921000B (zh) 2012-07-18
JP4749089B2 (ja) 2011-08-17
TWI421873B (zh) 2014-01-01
US20110110166A1 (en) 2011-05-12

Similar Documents

Publication Publication Date Title
KR101221787B1 (ko) 반도체 장치
US7948784B2 (en) Semiconductor memory device having vertical transistors
US7035161B2 (en) Semiconductor integrated circuit
JP2007059026A5 (enExample)
CN112116930A (zh) 在存储器模块的独立层上传送数据信号以及相关方法、系统和设备
US7782654B2 (en) Static random access memory device
JP2002015579A (ja) 比較的多数の内部データ・ラインを持つ高速メモリ回路用のアーキテクチャ
US7161867B2 (en) Semiconductor memory device
KR101324895B1 (ko) 메모리
US20060262631A1 (en) Bank selection signal control circuit for use in semiconductor memory device, and bank selection control method
US6370079B1 (en) Integrated circuits having reduced timing skew among signals transmitted therein using opposingly arranged selection circuits
US7433259B2 (en) Semiconductor memory device having layered bit line structure
US20100103757A1 (en) Semiconductor device
US6477074B2 (en) Semiconductor memory integrated circuit having high-speed data read and write operations
JP4956087B2 (ja) 半導体記憶装置
KR100308066B1 (ko) 데이터 버스 라인 제어회로
KR100489355B1 (ko) 노이즈감소를위한메모리소자
US20150380060A1 (en) Semiconductor device
KR100682678B1 (ko) 시간 제어식 판독 액세스 방식의 집적 다이나믹 반도체 메모리
KR100214483B1 (ko) 다 비트 입출력을 위한 디램
KR0142154B1 (ko) 동작전류를 감소시킬 수 있는 반도체 메모리 장치
CN118430604A (zh) 存储阵列、存储装置及电子设备
US20120039144A1 (en) Semiconductor device with shortened data read time
JP2008084484A (ja) 半導体記憶装置
JP2009009625A (ja) 半導体記憶装置

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

N231 Notification of change of applicant
PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

A201 Request for examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

FPAY Annual fee payment

Payment date: 20151217

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20170108

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20170108