CN1921000B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN1921000B
CN1921000B CN2006101256650A CN200610125665A CN1921000B CN 1921000 B CN1921000 B CN 1921000B CN 2006101256650 A CN2006101256650 A CN 2006101256650A CN 200610125665 A CN200610125665 A CN 200610125665A CN 1921000 B CN1921000 B CN 1921000B
Authority
CN
China
Prior art keywords
circuit
output
memory cell
input
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2006101256650A
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English (en)
Chinese (zh)
Other versions
CN1921000A (zh
Inventor
宫西笃史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of CN1921000A publication Critical patent/CN1921000A/zh
Application granted granted Critical
Publication of CN1921000B publication Critical patent/CN1921000B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Memories (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
CN2006101256650A 2005-08-26 2006-08-25 半导体装置 Expired - Fee Related CN1921000B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2005246408A JP4749089B2 (ja) 2005-08-26 2005-08-26 半導体装置
JP2005-246408 2005-08-26
JP2005246408 2005-08-26

Publications (2)

Publication Number Publication Date
CN1921000A CN1921000A (zh) 2007-02-28
CN1921000B true CN1921000B (zh) 2012-07-18

Family

ID=37778692

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2006101256650A Expired - Fee Related CN1921000B (zh) 2005-08-26 2006-08-25 半导体装置

Country Status (5)

Country Link
US (3) US20070047283A1 (enExample)
JP (1) JP4749089B2 (enExample)
KR (1) KR101221787B1 (enExample)
CN (1) CN1921000B (enExample)
TW (1) TWI421873B (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009238332A (ja) 2008-03-27 2009-10-15 Renesas Technology Corp 半導体記憶装置
US9472268B2 (en) * 2010-07-16 2016-10-18 Texas Instruments Incorporated SRAM with buffered-read bit cells and its testing
US8837250B2 (en) * 2010-07-20 2014-09-16 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for word line decoder layout
US10249361B2 (en) * 2014-01-14 2019-04-02 Nvidia Corporation SRAM write driver with improved drive strength
US9589611B2 (en) 2015-04-01 2017-03-07 Semiconductor Energy Laboratory Co., Ltd. Memory device, semiconductor device, and electronic device
US10854284B1 (en) 2016-12-06 2020-12-01 Gsi Technology, Inc. Computational memory cell and processing array device with ratioless write port
US10847212B1 (en) 2016-12-06 2020-11-24 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers
US10847213B1 (en) 2016-12-06 2020-11-24 Gsi Technology, Inc. Write data processing circuits and methods associated with computational memory cells
US10770133B1 (en) 2016-12-06 2020-09-08 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits
US10891076B1 (en) 2016-12-06 2021-01-12 Gsi Technology, Inc. Results processing circuits and methods associated with computational memory cells
US10998040B2 (en) 2016-12-06 2021-05-04 Gsi Technology, Inc. Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
US10777262B1 (en) 2016-12-06 2020-09-15 Gsi Technology, Inc. Read data processing circuits and methods associated memory cells
US10943648B1 (en) 2016-12-06 2021-03-09 Gsi Technology, Inc. Ultra low VDD memory cell with ratioless write port
US11227653B1 (en) 2016-12-06 2022-01-18 Gsi Technology, Inc. Storage array circuits and methods for computational memory cells
US10521229B2 (en) 2016-12-06 2019-12-31 Gsi Technology, Inc. Computational memory cell and processing array device using memory cells
US10860320B1 (en) 2016-12-06 2020-12-08 Gsi Technology, Inc. Orthogonal data transposition system and method during data transfers to/from a processing array
US11631465B2 (en) 2018-07-03 2023-04-18 Samsung Electronics Co., Ltd. Non-volatile memory device
CN110675907B (zh) * 2018-07-03 2024-08-23 三星电子株式会社 非易失性存储器装置和在其内部传输数据的方法
CN109885154B (zh) * 2019-02-28 2023-06-23 江西天漪半导体有限公司 一种带旁路通道的低功耗寄存器
US10958272B2 (en) 2019-06-18 2021-03-23 Gsi Technology, Inc. Computational memory cell and processing array device using complementary exclusive or memory cells
US10877731B1 (en) 2019-06-18 2020-12-29 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features
US10930341B1 (en) 2019-06-18 2021-02-23 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5701267A (en) * 1995-08-18 1997-12-23 Mitsubishi Electric Engineering Co., Ltd. Semiconductor storage device with macro-cell with monitoring of input data
US20040159882A1 (en) * 2003-02-19 2004-08-19 Takahiro Kawata Semiconductor device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0329185A (ja) * 1989-06-26 1991-02-07 Nec Corp デュアルポートメモリー装置
JPH04356793A (ja) * 1990-08-18 1992-12-10 Mitsubishi Electric Corp 半導体記憶装置
JPH04205787A (ja) * 1990-11-29 1992-07-27 Seiko Epson Corp マルチポートメモリ
JPH0574198A (ja) 1991-09-13 1993-03-26 Sony Corp テスト回路を備えたメモリ装置
JP3689435B2 (ja) * 1992-12-24 2005-08-31 株式会社リコー シリアル記憶装置
JP3691170B2 (ja) * 1996-08-30 2005-08-31 株式会社ルネサステクノロジ テスト回路
JP3226886B2 (ja) * 1999-01-29 2001-11-05 エヌイーシーマイクロシステム株式会社 半導体記憶装置とその制御方法
JP2001023400A (ja) 1999-07-07 2001-01-26 Hitachi Ltd 半導体装置およびその不良解析方法
JP3835220B2 (ja) * 2001-08-31 2006-10-18 セイコーエプソン株式会社 半導体記憶装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5701267A (en) * 1995-08-18 1997-12-23 Mitsubishi Electric Engineering Co., Ltd. Semiconductor storage device with macro-cell with monitoring of input data
US20040159882A1 (en) * 2003-02-19 2004-08-19 Takahiro Kawata Semiconductor device

Also Published As

Publication number Publication date
US20090185431A1 (en) 2009-07-23
US7898896B2 (en) 2011-03-01
CN1921000A (zh) 2007-02-28
US20070047283A1 (en) 2007-03-01
KR20070024358A (ko) 2007-03-02
TW200710864A (en) 2007-03-16
JP2007059026A (ja) 2007-03-08
JP4749089B2 (ja) 2011-08-17
KR101221787B1 (ko) 2013-01-11
TWI421873B (zh) 2014-01-01
US20110110166A1 (en) 2011-05-12

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C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: RENESAS ELECTRONICS CO., LTD.

Free format text: FORMER OWNER: RENESAS TECHNOLOGY CORP.

Effective date: 20100925

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20100925

Address after: Kawasaki, Kanagawa, Japan

Applicant after: Renesas Electronics Corporation

Address before: Tokyo, Japan, Japan

Applicant before: Renesas Technology Corp.

C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120718

Termination date: 20130825