KR101060862B1 - 인터포저 및 그의 제조방법 - Google Patents
인터포저 및 그의 제조방법 Download PDFInfo
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- KR101060862B1 KR101060862B1 KR1020090086614A KR20090086614A KR101060862B1 KR 101060862 B1 KR101060862 B1 KR 101060862B1 KR 1020090086614 A KR1020090086614 A KR 1020090086614A KR 20090086614 A KR20090086614 A KR 20090086614A KR 101060862 B1 KR101060862 B1 KR 101060862B1
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- wiring layer
- layer
- insulating plate
- forming
- upper wiring
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- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000010410 layer Substances 0.000 claims abstract description 118
- 239000011241 protective layer Substances 0.000 claims abstract description 28
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052802 copper Inorganic materials 0.000 claims abstract description 19
- 239000010949 copper Substances 0.000 claims abstract description 19
- 238000001465 metallisation Methods 0.000 claims abstract description 15
- 239000011347 resin Substances 0.000 claims abstract description 10
- 229920005989 resin Polymers 0.000 claims abstract description 10
- 238000010297 mechanical methods and process Methods 0.000 claims abstract description 5
- 238000005553 drilling Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 18
- 239000000919 ceramic Substances 0.000 claims description 7
- 238000002161 passivation Methods 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000006260 foam Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/0979—Redundant conductors or connections, i.e. more than one current path between two points
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10378—Interposers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
- H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Claims (10)
- 레이저 또는 드릴링과 같은 기계적인 방법으로 형성된 비아 홀에 도전재가 채워져 비아가 형성된, 레진을 포함하는 절연판;상기 절연판의 상면에 설계된 회로 패턴에 따라 상기 비아와 전기적으로 연결되도록 형성되는 제1상측재배선층;상기 제1상측재배선층의 일부가 노출되도록 적층되어 상기 제1상측재배선층을 보호하는 제1상측보호층;상기 제1상측재배선층과 전기적으로 연결되며 설계된 회로 패턴에 따라 적층된 제2상측재배선층;상기 제2상측재배선층의 일부가 노출되도록 적층되어 상기 제2상측재배선층을 보호하는 제2상측보호층; 및상기 제2상측재배선층의 노출된 부분에 형성되는 언더 범프 메탈라이제이션(under bump metalization, UBM);을 포함하는 인터포저.
- 제1항에 있어서,상기 절연판의 하면에 설계된 회로 패턴에 따라 상기 비아와 전기적으로 연결되도록 형성되는 하측재배선층;상기 하측재배선층의 일부가 노출되도록 적층되어 상기 하측재배선층을 보호 하는 하측보호층; 및상기 하측재배선층의 노출된 부분에 형성되는 언더 범프 메탈라이제이션(UBM);을 더 포함하는 것을 특징으로 하는 인터포저.
- 레진 또는 세라믹을 포함하는 절연판에 비아 홀을 형성하는 단계;상기 절연판의 상면에 제1상측재배선층 및 하면에 하측재배선층 형성을 위한 레지스트를 동시에 형성하는 단계;구리를 도금하여 상기 비아 홀 충전, 및 설계된 회로 패턴에 따라 상기 제1상측재배선층 및 하측재배선층 형성을 동시에 수행하는 단계; 및상기 제1상측재배선층 및 하측재배선층의 일부가 노출되도록 제1상측보호층 및 하측보호층을 형성하는 단계;를 포함하는 인터포저 제조방법.
- 제3항에 있어서,상기 제1상측보호층 및 하측보호층 형성 후 노출된 상기 제1상측재배선층 및 하측재배선층에 언더 범프 메탈라이제이션(UBM)을 형성하는 단계;를 더 포함하는 것을 특징으로 하는 인터포저 제조방법.
- 제3항에 있어서,상기 절연판의 상면에 설계된 회로 패턴에 따라 제2상측재배선층을 형성하고, 상기 제2상측재배선층의 일부가 노출되도록 제2상측보호층을 형성하는 단계;를 더 포함하는 것을 특징으로 하는 인터포저 제조방법.
- 제5항에 있어서,상기 제2상측보호층 형성 후 노출된 상기 제2상측재배선층에 언더 범프 메탈라이제이션(UBM)을 형성하는 단계;를 더 포함하는 것을 특징으로 하는 인터포저 제조방법.
- 제5항에 있어서,상기 제2상측재배선층 및 제2상측보호층을 형성하는 단계는,파인 피치 구현을 위하여 반도체 공정을 이용하여 수행되는 것임을 특징으로 하는 인터포저 제조방법.
- 제3항에 있어서,상기 절연판에 비아 홀을 형성하는 단계는,상기 절연판에 홀을 형성한 후 상기 절연판 내부의 레진 또는 세라믹이 노출된 부분에 시드레이어를 형성하는 것임을 특징으로 하는 인터포저 제조방법.
- 제3항에 있어서,상기 구리를 도금하여 상기 비아 홀 충전, 및 설계된 회로 패턴에 따라 상기 제1상측재배선층 및 하측재배선층 형성을 동시에 수행하는 단계는,상기 절연판의 양면 및 상기 비아 홀에 구리를 도금한 후 상기 레지스트를 제거하는 것임을 특징으로 하는 인터포저 제조방법.
- 제3항 내지 제9항 중 어느 한항에 있어서,상기 절연판은 양면에 구리로 형성된 층이 적층된 동박적층판(Copper Clad Laminate, CCL)인 것을 특징으로 하는 인터포저 제조방법.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020090086614A KR101060862B1 (ko) | 2009-09-14 | 2009-09-14 | 인터포저 및 그의 제조방법 |
US12/654,372 US20110061911A1 (en) | 2009-09-14 | 2009-12-17 | Interposer and method for manufacturing the same |
US13/632,614 US9196506B2 (en) | 2009-09-14 | 2012-10-01 | Method for manufacturing interposer |
Applications Claiming Priority (1)
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KR1020090086614A KR101060862B1 (ko) | 2009-09-14 | 2009-09-14 | 인터포저 및 그의 제조방법 |
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KR20110028959A KR20110028959A (ko) | 2011-03-22 |
KR101060862B1 true KR101060862B1 (ko) | 2011-08-31 |
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KR1020090086614A KR101060862B1 (ko) | 2009-09-14 | 2009-09-14 | 인터포저 및 그의 제조방법 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016093520A3 (ko) * | 2014-12-11 | 2016-07-28 | 엘지이노텍 주식회사 | 배선용 인터포저 및 이를 구비하는 전자 모듈 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8847380B2 (en) * | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
KR101431918B1 (ko) * | 2012-12-31 | 2014-08-19 | 삼성전기주식회사 | 인쇄회로기판 및 인쇄회로기판의 표면처리방법 |
US9401345B2 (en) | 2014-09-01 | 2016-07-26 | Freescale Semiconductor, Inc. | Semiconductor device package with organic interposer |
CN105470210B (zh) * | 2014-09-12 | 2018-04-10 | 旺宏电子股份有限公司 | 半导体装置及其制造方法 |
JP6341822B2 (ja) * | 2014-09-26 | 2018-06-13 | 三菱電機株式会社 | 半導体装置 |
CN105722299B (zh) * | 2014-12-03 | 2018-08-31 | 恒劲科技股份有限公司 | 中介基板及其制法 |
US9269659B1 (en) | 2015-01-08 | 2016-02-23 | Freescale Semiconductor, Inc. | Interposer with overmolded vias |
CN104701192B (zh) * | 2015-03-11 | 2018-05-22 | 华进半导体封装先导技术研发中心有限公司 | 保护超薄硅基板的结构和制备工艺 |
KR102386969B1 (ko) * | 2019-04-01 | 2022-04-18 | 주식회사 아모센스 | 다층구조의 인터포저 및 그 제조방법 |
WO2020204493A1 (ko) * | 2019-04-01 | 2020-10-08 | 주식회사 아모센스 | 인터포저 및 그 제조방법 |
KR102387826B1 (ko) * | 2019-04-01 | 2022-04-18 | 주식회사 아모센스 | 인터포저 및 그 제조방법 |
US11830806B2 (en) * | 2021-04-29 | 2023-11-28 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method of manufacturing the same |
CN113035833B (zh) * | 2021-05-28 | 2021-09-28 | 浙江集迈科微电子有限公司 | 多层布线转接板及其制备方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2008013054A1 (fr) | 2006-07-24 | 2008-01-31 | Ibiden Co., Ltd. | Interposeur et dispositif électronique utilisant celui-ci |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4963697A (en) * | 1988-02-12 | 1990-10-16 | Texas Instruments Incorporated | Advanced polymers on metal printed wiring board |
USRE40947E1 (en) * | 1997-10-14 | 2009-10-27 | Ibiden Co., Ltd. | Multilayer printed wiring board and its manufacturing method, and resin composition for filling through-hole |
KR100833723B1 (ko) * | 1999-10-26 | 2008-05-29 | 이비덴 가부시키가이샤 | 다층프린트배선판 및 다층프린트배선판의 제조 방법 |
JP2003069185A (ja) * | 2001-08-29 | 2003-03-07 | Hitachi Ltd | キャパシタを内蔵した回路基板 |
US7371975B2 (en) * | 2002-12-18 | 2008-05-13 | Intel Corporation | Electronic packages and components thereof formed by substrate-imprinting |
KR100971104B1 (ko) | 2004-02-24 | 2010-07-20 | 이비덴 가부시키가이샤 | 반도체 탑재용 기판 |
JP5311609B2 (ja) | 2007-10-30 | 2013-10-09 | 新光電気工業株式会社 | シリコンインターポーザの製造方法およびシリコンインターポーザと、これを用いた半導体装置用パッケージおよび半導体装置 |
-
2009
- 2009-09-14 KR KR1020090086614A patent/KR101060862B1/ko active IP Right Grant
- 2009-12-17 US US12/654,372 patent/US20110061911A1/en not_active Abandoned
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2012
- 2012-10-01 US US13/632,614 patent/US9196506B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008013054A1 (fr) | 2006-07-24 | 2008-01-31 | Ibiden Co., Ltd. | Interposeur et dispositif électronique utilisant celui-ci |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016093520A3 (ko) * | 2014-12-11 | 2016-07-28 | 엘지이노텍 주식회사 | 배선용 인터포저 및 이를 구비하는 전자 모듈 |
Also Published As
Publication number | Publication date |
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US20110061911A1 (en) | 2011-03-17 |
US20130029031A1 (en) | 2013-01-31 |
KR20110028959A (ko) | 2011-03-22 |
US9196506B2 (en) | 2015-11-24 |
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