KR101004423B1 - 재결합 영역을 갖는 soi 전계 효과 트랜지스터 소자 및 그 제조 방법 - Google Patents
재결합 영역을 갖는 soi 전계 효과 트랜지스터 소자 및 그 제조 방법 Download PDFInfo
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Abstract
Description
Claims (16)
- 기판에 형성되는 전계 효과 트랜지스터(300)로서,절연층(310)이 형성되어 있는 기판(301)과;상기 절연층(310) 위에 형성된 결정 활성 영역(302)과, 여기서 상기 결정 활성 영역(302)은 제 1 농도의 국부화된 재결합 중심들을 갖는 제 1 영역(321) 및 제 2 농도의 국부화된 재결합 중심들을 갖는 제 2 영역(320)을 갖고, 상기 제 2 농도는 상기 제 1 농도 보다 높으며;드레인 영역(304) 및 소스 영역(303)과; 그리고게이트 절연층(307)에 의해 상기 활성 영역(302)으로부터 전기적으로 절연되는 게이트 전극(306)을 포함하며,여기서, 상기 제 2 영역(320)은 조성, 층 두께 및 물질 타입중 적어도 하나에 의해 서로 다른 복수의 서브층들(320a, 320b, 320c, 320d)을 포함하고,상기 국부화된 재결합 중심들은 실질적으로 상기 제 2 영역(320) 내의 점 결함들로 이루어지는 것을 특징으로 하는 전계 효과 트랜지스터.
- 제 1 항에 있어서,상기 점 결함들은 실질적으로 장력이 걸리지 않은 반도체층에 포함되는 것을 특징으로 하는 전계 효과 트랜지스터.
- 제 1 항에 있어서,상기 제 2 영역(320)의 밴드갭 에너지는 상기 제 1 영역(321)의 밴드갭 에너지 보다 낮은 것을 특징으로 하는 전계 효과 트랜지스터.
- 제 1 항에 있어서,상기 제 2 영역(320)은 상기 절연층(310)과 접촉하는 것을 특징으로 하는 전계 효과 트랜지스터.
- 제 1 항에 있어서,상기 제 2 영역(320)은 상기 소스 영역(303)과 접촉하는 것을 특징으로 하는 전계 효과 트랜지스터.
- 제 1 항에 있어서,상기 제 2 영역(320)은 상기 드레인 영역(304)과 접촉하는 것을 특징으로 하는 전계 효과 트랜지스터.
- 제 1 항에 있어서,상기 제 2 영역(320)은 적어도 2개의 다른 물질들로 이루어지는 것을 특징으로 하는 전계 효과 트랜지스터.
- 제 6 항에 있어서,상기 제 2 영역(320)은 게르마늄으로 이루어지는 것을 특징으로 하는 전계 효과 트랜지스터.
- 제 8 항에 있어서,상기 제 2 영역(320)은 SixGe1-x 형태의 화합물로 이루어지고, 상기 x는 0.2 > x > 0.8의 범위를 갖는 것을 특징으로 하는 전계 효과 트랜지스터.
- 제 1 항에 있어서,상기 점 결함들의 농도는 1012/cm3 보다 높은 것을 특징으로 하는 전계 효과 트랜지스터.
- 기판에 트랜지스터 소자를 형성하는 방법으로서,절연층(310)이 형성되어 있는 기판(301)을 제공하는 단계와;제 1, 2 결정 반도체층들(321, 320)을 형성하는 단계와, 여기서 상기 제 1, 2 결정 반도체층들은 서로 다른 격자 상수를 가짐으로써 상기 제 2 결정 반도체층(320)에 장력을 야기시키며;상기 제 1, 2 결정 반도체층들(321, 320) 내에서 이들 위에 트랜지스터 소자를 형성하는 단계와; 그리고상기 트랜지스터 소자를 형성하는 동안 1개 또는 그 이상의 열처리들을 수행하는 단계를 포함하며, 상기 열처리들에 의해 상기 장력이 감소되고, 상기 제 2 결정 반도체층(320)의 점 결함들의 농도가 상기 제 1 결정 반도체층(321)의 점 결함들의 농도 보다 높아지게 되며;상기 제 2 결정 반도체층(320)을 형성하는 단계는 조성, 층 두께 및 물질 타입중 적어도 하나에 의해 서로 다른 복수의 서브층들(320a, 320b, 320c, 320d)을 형성하는 단계를 포함하는 것을 특징으로 하는 트랜지스터 소자를 형성하는 방법.
- 제 11 항에 있어서,상기 제 1, 2 결정 반도체층들(321, 320)을 형성하는 단계는:결정 도너 기판 위에 상기 제 2 결정 반도체층(320)을 에피택셜 성장시키는 단계와; 그리고상기 절연층(310) 위에 상기 제 2 결정 반도체층(320)이 위치한 상태로, 상기 기판(301)과 상기 결정 도너 기판을 서로 결합하는 단계를 포함하는 것을 특징으로 하는 트랜지스터 소자를 형성하는 방법.
- 제 11 항에 있어서,상기 제 2 결정 반도체층(320)은 SixGe1-x의 조성을 갖는 실리콘 게르마늄층으로 이루어지고, 상기 x는 0.2 > x > 0.8의 범위를 갖는 것을 특징으로 하는 트랜지스터 소자를 형성하는 방법.
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DE10229003.2A DE10229003B4 (de) | 2002-06-28 | 2002-06-28 | Ein Verfahren zur Herstellung eines SOI-Feldeffekttransistorelements mit einem Rekombinationsgebiet |
DE10229003.3 | 2002-06-28 | ||
US10/391,255 | 2003-03-18 | ||
US10/391,255 US6812074B2 (en) | 2002-06-28 | 2003-03-18 | SOI field effect transistor element having a recombination region and method of forming same |
PCT/US2003/020791 WO2004004015A2 (en) | 2002-06-28 | 2003-06-24 | Soi field effect transistor element having a recombination region and method of forming same |
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US20060048700A1 (en) * | 2002-09-05 | 2006-03-09 | Wanlass Mark W | Method for achieving device-quality, lattice-mismatched, heteroepitaxial active layers |
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US6979622B1 (en) * | 2004-08-24 | 2005-12-27 | Freescale Semiconductor, Inc. | Semiconductor transistor having structural elements of differing materials and method of formation |
US7064414B2 (en) * | 2004-11-12 | 2006-06-20 | International Business Machines Corporation | Heater for annealing trapped charge in a semiconductor device |
US20080121932A1 (en) | 2006-09-18 | 2008-05-29 | Pushkar Ranade | Active regions with compatible dielectric layers |
US20070132034A1 (en) * | 2005-12-14 | 2007-06-14 | Giuseppe Curello | Isolation body for semiconductor devices and method to form the same |
DE102006019935B4 (de) * | 2006-04-28 | 2011-01-13 | Advanced Micro Devices, Inc., Sunnyvale | SOI-Transistor mit reduziertem Körperpotential und ein Verfahren zur Herstellung |
US7521776B2 (en) | 2006-12-29 | 2009-04-21 | International Business Machines Corporation | Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers |
KR101006524B1 (ko) * | 2008-09-19 | 2011-01-07 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조방법 |
CN101872737A (zh) * | 2010-01-28 | 2010-10-27 | 中国科学院上海微系统与信息技术研究所 | 一种抑制soi浮体效应的mos结构及其制作方法 |
CN113611737A (zh) * | 2021-08-05 | 2021-11-05 | 西安电子科技大学 | 基于22nm工艺条件的抗辐照FDSOI场效应管及其制备方法 |
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2002
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2003
- 2003-03-18 US US10/391,255 patent/US6812074B2/en not_active Expired - Lifetime
- 2003-06-24 KR KR1020047021322A patent/KR101004423B1/ko active IP Right Grant
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US20020058361A1 (en) * | 1997-06-19 | 2002-05-16 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR101632849B1 (ko) | 2015-12-31 | 2016-06-23 | 전라남도 | 새꼬막 채묘 및 중간육성방법 |
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DE10229003B4 (de) | 2014-02-13 |
US6812074B2 (en) | 2004-11-02 |
KR20050013163A (ko) | 2005-02-02 |
DE10229003A1 (de) | 2004-01-29 |
US20040000691A1 (en) | 2004-01-01 |
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