KR100903472B1 - 웨이퍼로부터 반도체 다이를 분리하는 방법 - Google Patents
웨이퍼로부터 반도체 다이를 분리하는 방법 Download PDFInfo
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- KR100903472B1 KR100903472B1 KR1020020044126A KR20020044126A KR100903472B1 KR 100903472 B1 KR100903472 B1 KR 100903472B1 KR 1020020044126 A KR1020020044126 A KR 1020020044126A KR 20020044126 A KR20020044126 A KR 20020044126A KR 100903472 B1 KR100903472 B1 KR 100903472B1
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Abstract
Description
Claims (14)
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- 상부면 및 하부면을 갖고 대응하는 다이 영역에 복수의 전기 회로를 갖는 웨이퍼로부터 다이들을 분리하는 방법에 있어서,상기 웨이퍼에서 상기 웨이퍼의 다이 영역들 사이에 위치하고 상기 상부면으로부터 상기 하부면을 향하여 상기 웨이퍼 내부로 확장하는 채널을 에칭하는 단계;상기 웨이퍼의 다이 영역의 상기 상부면상에 캐리어 테이프를 장착하는 단계; 및상기 채널을 노출시키고 상기 다이들을 서로 분리시키기 위해 상기 웨이퍼의 하부면으로부터 패턴에 따라 재료를 제거하는 단계를 포함하며,상기 웨이퍼에서 채널을 에칭하는 단계는 반응성 이온 에칭 공정을 이용하여 상기 웨이퍼의 상부면으로부터 재료를 제거하는 단계를 포함하고,상기 웨이퍼의 하부면으로부터 재료를 제거하는 단계는 연삭 및 에칭 중 적어도 하나를 포함하고,상기 웨이퍼의 하부면으로부터 재료를 제거하는 단계는 상기 웨이퍼의 하부면에서 등고면(contoured surface)을 에칭하는 단계를 포함하고,상기 등고면을 에칭하는 단계는 상기 등고면을 생성하도록 상기 웨이퍼의 하부면을 선택적으로 에칭하는 단계를 포함하고,상기 웨이퍼의 하부면을 선택적으로 에칭하는 단계는,항에칭 재료를 이용하여 상기 웨이퍼의 하부면에 패턴을 도포시키는 단계; 및상기 등고면을 생성하도록 플라즈마를 이용하여 상기 하부면 패턴을 선택적으로 에칭하는 단계를 포함하는 방법.
- 제6항에 있어서, 상기 웨이퍼의 하부면에 패턴을 도포하는 단계는 상기 웨이퍼의 하부면상에 도트 패턴으로 폴리머 방울들을 분사하는 단계를 포함하는 방법.
- 제7항에 있어서, 상기 폴리머 방울들은 상기 웨이퍼의 에칭속도와 양립될 수 있는 에칭속도를 가지며, 상기 하부면 패턴을 선택적으로 에칭하는 단계는 상기 채널이 노출될 때까지 상기 하부면상에서 무지향성(non-directional) 에칭을 수행하 는 단계를 포함하는 방법.
- 삭제
- 삭제
- 삭제
- 상부면 및 하부면을 갖고 대응하는 다이 영역에 복수의 전기 회로를 갖는 웨이퍼로부터 다이들을 분리하는 방법에 있어서,상기 웨이퍼에서 상기 웨이퍼의 다이 영역들 사이에 위치하고 상기 상부면으로부터 상기 하부면을 향하여 상기 웨이퍼 내부로 확장하는 채널을 에칭하는 단계;상기 웨이퍼의 다이 영역의 상기 상부면상에 캐리어 테이프를 장착하는 단계; 및상기 채널을 노출시키고 상기 다이들을 서로 분리시키기 위해 상기 웨이퍼의 하부면으로부터 패턴에 따라 재료를 제거하는 단계를 포함하며,상기 웨이퍼의 하부면으로부터 재료를 제거하는 단계는 연삭 및 에칭 중 적어도 하나를 포함하고,상기 웨이퍼의 하부면으로부터 재료를 제거하는 단계는 상기 웨이퍼의 하부면에서 등고면을 에칭하는 단계를 포함하고,상기 등고면을 에칭하는 단계는 상기 등고면을 생성하도록 상기 웨이퍼의 하부면을 선택적으로 에칭하는 단계를 포함하고,상기 웨이퍼의 하부면을 선택적으로 에칭하는 단계는,항에칭 재료를 이용하여 상기 웨이퍼의 하부면에 패턴을 도포시키는 단계; 및상기 등고면을 생성하도록 플라즈마를 이용하여 상기 하부면 패턴을 선택적으로 에칭하는 단계를 포함하는 방법.
- 제12항에 있어서, 상기 웨이퍼의 하부면에 패턴을 도포하는 단계는 상기 웨이퍼의 하부면상에 도트 패턴으로 폴리머 방울들을 분사하는 단계를 포함하는 방법.
- 제13항에 있어서, 상기 폴리머 방울들은 상기 웨이퍼의 에칭속도와 양립될 수 있는 에칭속도를 가지며, 상기 하부면 패턴을 선택적으로 에칭하는 단계는 상기 채널이 노출될 때까지 상기 하부면상에서 무지향성 에칭을 수행하는 단계를 포함하는 방법.
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Families Citing this family (83)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6686225B2 (en) * | 2001-07-27 | 2004-02-03 | Texas Instruments Incorporated | Method of separating semiconductor dies from a wafer |
JP3530158B2 (ja) * | 2001-08-21 | 2004-05-24 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
DE10245631B4 (de) * | 2002-09-30 | 2022-01-20 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Halbleiterbauelement |
JP2004130579A (ja) * | 2002-10-09 | 2004-04-30 | Sony Corp | 液体吐出ヘッド、液体吐出装置及び液体吐出ヘッドの製造方法 |
US6897128B2 (en) * | 2002-11-20 | 2005-05-24 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing semiconductor device, plasma processing apparatus and plasma processing method |
JP2006509371A (ja) * | 2002-12-09 | 2006-03-16 | アドバンスド インターコネクト テクノロジーズ リミテッド | 露出された集積回路装置を有するパッケージ |
JP3891123B2 (ja) * | 2003-02-06 | 2007-03-14 | セイコーエプソン株式会社 | 半導体装置、電子デバイス、電子機器、及び半導体装置の製造方法 |
JP4110992B2 (ja) * | 2003-02-07 | 2008-07-02 | セイコーエプソン株式会社 | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
JP2004281818A (ja) * | 2003-03-17 | 2004-10-07 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、キャリア基板の製造方法、半導体装置の製造方法および電子デバイスの製造方法 |
JP4069771B2 (ja) * | 2003-03-17 | 2008-04-02 | セイコーエプソン株式会社 | 半導体装置、電子機器および半導体装置の製造方法 |
JP2004281920A (ja) * | 2003-03-18 | 2004-10-07 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
JP2004281919A (ja) * | 2003-03-18 | 2004-10-07 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
JP4096774B2 (ja) * | 2003-03-24 | 2008-06-04 | セイコーエプソン株式会社 | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法 |
JP2004349495A (ja) * | 2003-03-25 | 2004-12-09 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器および半導体装置の製造方法 |
JP4234630B2 (ja) * | 2003-05-29 | 2009-03-04 | 古河電気工業株式会社 | 貫通構造を有する薄膜化回路基板の製造方法と保護用粘着テープ |
US20050064679A1 (en) * | 2003-09-19 | 2005-03-24 | Farnworth Warren M. | Consolidatable composite materials, articles of manufacture formed therefrom, and fabrication methods |
US20050064683A1 (en) * | 2003-09-19 | 2005-03-24 | Farnworth Warren M. | Method and apparatus for supporting wafers for die singulation and subsequent handling |
US7713841B2 (en) * | 2003-09-19 | 2010-05-11 | Micron Technology, Inc. | Methods for thinning semiconductor substrates that employ support structures formed on the substrates |
DE10350036B4 (de) * | 2003-10-27 | 2014-01-23 | Robert Bosch Gmbh | Verfahren zum Vereinzeln von Halbleiterchips und entsprechende Halbleiterchipanordnung |
US7244665B2 (en) | 2004-04-29 | 2007-07-17 | Micron Technology, Inc. | Wafer edge ring structures and methods of formation |
US7547978B2 (en) * | 2004-06-14 | 2009-06-16 | Micron Technology, Inc. | Underfill and encapsulation of semiconductor assemblies with materials having differing properties |
US7329555B1 (en) | 2004-07-20 | 2008-02-12 | National Semiconductor Corporation | Method of selectively forming MEMS-based semiconductor devices at the end of a common fabrication process |
US20060046433A1 (en) * | 2004-08-25 | 2006-03-02 | Sterrett Terry L | Thinning semiconductor wafers |
US20060057777A1 (en) * | 2004-09-14 | 2006-03-16 | Howell William C | Separating die on a substrate to reduce backside chipping |
US7049208B2 (en) | 2004-10-11 | 2006-05-23 | Intel Corporation | Method of manufacturing of thin based substrate |
US7816182B2 (en) * | 2004-11-30 | 2010-10-19 | Stmicroelectronics Asia Pacific Pte. Ltd. | Simplified multichip packaging and package design |
JP4731241B2 (ja) * | 2005-08-02 | 2011-07-20 | 株式会社ディスコ | ウエーハの分割方法 |
DE102005050127B3 (de) * | 2005-10-18 | 2007-05-16 | Infineon Technologies Ag | Verfahren zum Aufbringen einer Struktur aus Fügematerial auf die Rückseiten von Halbleiterchips |
US7871899B2 (en) * | 2006-01-11 | 2011-01-18 | Amkor Technology, Inc. | Methods of forming back side layers for thinned wafers |
US7378293B2 (en) * | 2006-03-22 | 2008-05-27 | Texas Instruments Incorporated | MEMS fabrication method |
US20100155247A1 (en) * | 2006-03-29 | 2010-06-24 | Jie Cao | Radiation-curable rubber adhesive/sealant |
US7550778B2 (en) | 2006-05-17 | 2009-06-23 | Innovative Micro Technology | System and method for providing access to an encapsulated device |
KR100817059B1 (ko) * | 2006-09-11 | 2008-03-27 | 삼성전자주식회사 | 박형 반도체 패키지 제조방법 |
US20080153265A1 (en) * | 2006-12-21 | 2008-06-26 | Texas Instruments Incorporated | Semiconductor Device Manufactured Using an Etch to Separate Wafer into Dies and Increase Device Space on a Wafer |
US7585750B2 (en) * | 2007-05-04 | 2009-09-08 | Stats Chippac, Ltd. | Semiconductor package having through-hole via on saw streets formed with partial saw |
KR100863333B1 (ko) * | 2007-06-27 | 2008-10-15 | 주식회사 효광 | 기판 가공 방법 및 그로써 제작되는 칩 |
EP2015356A1 (en) * | 2007-07-13 | 2009-01-14 | PVA TePla AG | Method for singulation of wafers |
US7972902B2 (en) * | 2007-07-23 | 2011-07-05 | Samsung Electronics Co., Ltd. | Method of manufacturing a wafer including providing electrical conductors isolated from circuitry |
KR101185886B1 (ko) | 2007-07-23 | 2012-09-25 | 삼성전자주식회사 | 유니버설 배선 라인들을 포함하는 반도체 칩, 반도체패키지, 카드 및 시스템 |
US7989319B2 (en) * | 2007-08-07 | 2011-08-02 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
US8859396B2 (en) | 2007-08-07 | 2014-10-14 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
US7781310B2 (en) * | 2007-08-07 | 2010-08-24 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
US8012857B2 (en) * | 2007-08-07 | 2011-09-06 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
US7923298B2 (en) | 2007-09-07 | 2011-04-12 | Micron Technology, Inc. | Imager die package and methods of packaging an imager die on a temporary carrier |
US7943489B2 (en) * | 2008-09-25 | 2011-05-17 | Texas Instruments Incorporated | Bonded wafer assembly system and method |
US8257985B2 (en) | 2008-09-25 | 2012-09-04 | Texas Instruments Incorporated | MEMS device and fabrication method |
US7871857B1 (en) * | 2008-09-29 | 2011-01-18 | Integrated Device Technology, Inc. | Methods of forming multi-chip semiconductor substrates |
JPWO2010061470A1 (ja) * | 2008-11-28 | 2012-04-19 | セイコーインスツル株式会社 | ウエハおよびパッケージ製品の製造方法 |
CN102257612A (zh) * | 2008-12-18 | 2011-11-23 | 精工电子有限公司 | 圆片及封装件制品的制造方法 |
TWI513668B (zh) * | 2009-02-23 | 2015-12-21 | Seiko Instr Inc | 玻璃密封型封裝的製造方法及玻璃基板 |
TW201104736A (en) * | 2009-04-24 | 2011-02-01 | Henkel Corp | Dicing before grinding process for preparation of semiconductor |
CN102130025B (zh) * | 2009-11-16 | 2015-03-11 | 三星电子株式会社 | 晶片及其处理方法和制造半导体装置的方法 |
US9165833B2 (en) * | 2010-01-18 | 2015-10-20 | Semiconductor Components Industries, Llc | Method of forming a semiconductor die |
US9299664B2 (en) * | 2010-01-18 | 2016-03-29 | Semiconductor Components Industries, Llc | Method of forming an EM protected semiconductor die |
US20110175209A1 (en) * | 2010-01-18 | 2011-07-21 | Seddon Michael J | Method of forming an em protected semiconductor die |
US8384231B2 (en) * | 2010-01-18 | 2013-02-26 | Semiconductor Components Industries, Llc | Method of forming a semiconductor die |
US8294275B2 (en) * | 2010-02-12 | 2012-10-23 | Chao-Yen Lin | Chip package and method for forming the same |
US8409926B2 (en) | 2010-03-09 | 2013-04-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming insulating layer around semiconductor die |
EP2567401A4 (en) * | 2010-05-03 | 2013-12-25 | S3C Inc | METHOD FOR MINIMIZING SCALING DURING THE SEPARATION OF MEMS DEN ON A WAFER |
KR101560039B1 (ko) | 2010-06-08 | 2015-10-13 | 헨켈 아이피 앤드 홀딩 게엠베하 | 그라인딩 전의 다이싱 및 마이크로 제조된 웨이퍼들 상의 접착제의 코팅 |
TWI614816B (zh) * | 2010-06-22 | 2018-02-11 | 美國亞德諾半導體公司 | 用以蝕刻及分割蓋晶圓之方法 |
KR101997293B1 (ko) | 2011-02-01 | 2019-07-05 | 헨켈 아이피 앤드 홀딩 게엠베하 | 다이싱 테이프 상에 사전 절단 웨이퍼가 도포된 언더필 필름 |
KR101960982B1 (ko) | 2011-02-01 | 2019-07-15 | 헨켈 아이피 앤드 홀딩 게엠베하 | 사전 절단되어 웨이퍼상에 도포된 언더필 필름 |
JP2012186532A (ja) | 2011-03-03 | 2012-09-27 | Seiko Instruments Inc | ウエハ、パッケージの製造方法、及び圧電振動子 |
US8802545B2 (en) | 2011-03-14 | 2014-08-12 | Plasma-Therm Llc | Method and apparatus for plasma dicing a semi-conductor wafer |
US20120273935A1 (en) * | 2011-04-29 | 2012-11-01 | Stefan Martens | Semiconductor Device and Method of Making a Semiconductor Device |
US8828848B2 (en) * | 2011-12-16 | 2014-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Die structure and method of fabrication thereof |
US8952413B2 (en) | 2012-03-08 | 2015-02-10 | Micron Technology, Inc. | Etched trenches in bond materials for die singulation, and associated systems and methods |
US20130256843A1 (en) * | 2012-04-03 | 2013-10-03 | United Microelectronics Corporation | Wafer sawing method and wafer structure beneficial for performing the same |
KR20140009731A (ko) * | 2012-07-12 | 2014-01-23 | 삼성전자주식회사 | 방열부를 포함하는 반도체 칩 및 그 반도체 칩 제조 방법 |
US9484260B2 (en) | 2012-11-07 | 2016-11-01 | Semiconductor Components Industries, Llc | Heated carrier substrate semiconductor die singulation method |
US9136173B2 (en) | 2012-11-07 | 2015-09-15 | Semiconductor Components Industries, Llc | Singulation method for semiconductor die having a layer of material along one major surface |
KR102053349B1 (ko) | 2013-05-16 | 2019-12-06 | 삼성전자주식회사 | 반도체 패키지 |
US9418894B2 (en) | 2014-03-21 | 2016-08-16 | Semiconductor Components Industries, Llc | Electronic die singulation method |
US9385041B2 (en) | 2014-08-26 | 2016-07-05 | Semiconductor Components Industries, Llc | Method for insulating singulated electronic die |
TWI664668B (zh) | 2014-10-13 | 2019-07-01 | 新加坡商聯測總部私人有限公司 | 用於單一化半導體晶圓之方法 |
JP6490459B2 (ja) * | 2015-03-13 | 2019-03-27 | 古河電気工業株式会社 | ウェハ固定テープ、半導体ウェハの処理方法および半導体チップ |
US10948424B2 (en) * | 2016-03-02 | 2021-03-16 | Hitachi High-Tech Corporation | Defect inspection device, pattern chip, and defect inspection method |
US10366923B2 (en) | 2016-06-02 | 2019-07-30 | Semiconductor Components Industries, Llc | Method of separating electronic devices having a back layer and apparatus |
CN106024648B (zh) * | 2016-06-15 | 2020-02-07 | 华润微电子(重庆)有限公司 | 一种分立器件芯片正面及侧壁钝化方法 |
JP2018120687A (ja) * | 2017-01-24 | 2018-08-02 | 住友電装株式会社 | コネクタ |
US10373869B2 (en) | 2017-05-24 | 2019-08-06 | Semiconductor Components Industries, Llc | Method of separating a back layer on a substrate using exposure to reduced temperature and related apparatus |
US10818551B2 (en) | 2019-01-09 | 2020-10-27 | Semiconductor Components Industries, Llc | Plasma die singulation systems and related methods |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04297056A (ja) * | 1991-03-08 | 1992-10-21 | Sony Corp | 半導体装置の製造方法 |
US5904548A (en) * | 1996-11-21 | 1999-05-18 | Texas Instruments Incorporated | Trench scribe line for decreased chip spacing |
US5972781A (en) * | 1997-09-30 | 1999-10-26 | Siemens Aktiengesellschaft | Method for producing semiconductor chips |
JP2001035817A (ja) * | 1999-07-22 | 2001-02-09 | Toshiba Corp | ウェーハの分割方法及び半導体装置の製造方法 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3562058A (en) | 1967-05-16 | 1971-02-09 | Texas Instruments Inc | Method for breaking and separating substrate material |
DE2522346C3 (de) * | 1975-05-20 | 1978-10-26 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zum Herstellen von Halbleiterbauelementen |
KR920004514B1 (ko) | 1987-05-01 | 1992-06-08 | 스미도모덴기고오교오 가부시기가이샤 | 반도체소자 제조장치 |
US4903089A (en) * | 1988-02-02 | 1990-02-20 | Massachusetts Institute Of Technology | Vertical transistor device fabricated with semiconductor regrowth |
US5824569A (en) * | 1992-07-15 | 1998-10-20 | Micron Technology, Inc. | Semiconductor device having ball-bonded pads |
US6184063B1 (en) | 1996-11-26 | 2001-02-06 | Texas Instruments Incorporated | Method and apparatus for breaking and separating a wafer into die using a multi-radii dome |
US6114187A (en) * | 1997-01-11 | 2000-09-05 | Microfab Technologies, Inc. | Method for preparing a chip scale package and product produced by the method |
US6127245A (en) | 1997-02-04 | 2000-10-03 | Micron Technology, Inc. | Grinding technique for integrated circuits |
US5923995A (en) * | 1997-04-18 | 1999-07-13 | National Semiconductor Corporation | Methods and apparatuses for singulation of microelectromechanical systems |
US5863813A (en) * | 1997-08-20 | 1999-01-26 | Micron Communications, Inc. | Method of processing semiconductive material wafers and method of forming flip chips and semiconductor chips |
US6087199A (en) * | 1998-02-04 | 2000-07-11 | International Business Machines Corporation | Method for fabricating a very dense chip package |
US6448184B1 (en) * | 1998-06-25 | 2002-09-10 | Pacific Western Systems | Formation of diamond particle interconnects |
US6465329B1 (en) * | 1999-01-20 | 2002-10-15 | Amkor Technology, Inc. | Microcircuit die-sawing protector and method |
US6278181B1 (en) * | 1999-06-28 | 2001-08-21 | Advanced Micro Devices, Inc. | Stacked multi-chip modules using C4 interconnect technology having improved thermal management |
JP3455762B2 (ja) * | 1999-11-11 | 2003-10-14 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
JP4409014B2 (ja) * | 1999-11-30 | 2010-02-03 | リンテック株式会社 | 半導体装置の製造方法 |
US6184064B1 (en) * | 2000-01-12 | 2001-02-06 | Micron Technology, Inc. | Semiconductor die back side surface and method of fabrication |
US6717245B1 (en) * | 2000-06-02 | 2004-04-06 | Micron Technology, Inc. | Chip scale packages performed by wafer level processing |
KR100425934B1 (ko) * | 2000-12-29 | 2004-04-03 | 주식회사 하이닉스반도체 | 실리콘-게르마늄막 형성 방법 |
US6589809B1 (en) * | 2001-07-16 | 2003-07-08 | Micron Technology, Inc. | Method for attaching semiconductor components to a substrate using local UV curing of dicing tape |
US6686225B2 (en) * | 2001-07-27 | 2004-02-03 | Texas Instruments Incorporated | Method of separating semiconductor dies from a wafer |
DE10202881B4 (de) * | 2002-01-25 | 2007-09-20 | Infineon Technologies Ag | Verfahren zur Herstellung von Halbleiterchips mit einer Chipkantenschutzschicht, insondere für Wafer Level Packaging Chips |
-
2001
- 2001-07-27 US US09/917,534 patent/US6686225B2/en not_active Expired - Lifetime
-
2002
- 2002-07-23 JP JP2002214138A patent/JP2003086544A/ja active Pending
- 2002-07-26 TW TW091116723A patent/TW552676B/zh not_active IP Right Cessation
- 2002-07-26 KR KR1020020044126A patent/KR100903472B1/ko active IP Right Grant
-
2003
- 2003-12-17 US US10/739,237 patent/US20040129451A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04297056A (ja) * | 1991-03-08 | 1992-10-21 | Sony Corp | 半導体装置の製造方法 |
US5904548A (en) * | 1996-11-21 | 1999-05-18 | Texas Instruments Incorporated | Trench scribe line for decreased chip spacing |
US5972781A (en) * | 1997-09-30 | 1999-10-26 | Siemens Aktiengesellschaft | Method for producing semiconductor chips |
JP2001035817A (ja) * | 1999-07-22 | 2001-02-09 | Toshiba Corp | ウェーハの分割方法及び半導体装置の製造方法 |
Also Published As
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TW552676B (en) | 2003-09-11 |
US6686225B2 (en) | 2004-02-03 |
US20030022465A1 (en) | 2003-01-30 |
JP2003086544A (ja) | 2003-03-20 |
US20040129451A1 (en) | 2004-07-08 |
KR20030010549A (ko) | 2003-02-05 |
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