KR100810012B1 - 격자 부정합 에피택셜 확장부와 소스 및 드레인 영역을갖는 변형 채널 cmos 트랜지스터의 구조 및 그 제조방법 - Google Patents
격자 부정합 에피택셜 확장부와 소스 및 드레인 영역을갖는 변형 채널 cmos 트랜지스터의 구조 및 그 제조방법 Download PDFInfo
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- KR100810012B1 KR100810012B1 KR1020067003154A KR20067003154A KR100810012B1 KR 100810012 B1 KR100810012 B1 KR 100810012B1 KR 1020067003154 A KR1020067003154 A KR 1020067003154A KR 20067003154 A KR20067003154 A KR 20067003154A KR 100810012 B1 KR100810012 B1 KR 100810012B1
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- semiconductor
- nfet
- pfet
- layer
- channel region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0172—Manufacturing their gate conductors
- H10D84/0174—Manufacturing their gate conductors the gate conductors being silicided
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0184—Manufacturing their gate sidewall spacers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/605,134 US6906360B2 (en) | 2003-09-10 | 2003-09-10 | Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions |
| US10/605,134 | 2003-09-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20060060691A KR20060060691A (ko) | 2006-06-05 |
| KR100810012B1 true KR100810012B1 (ko) | 2008-03-07 |
Family
ID=34225881
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020067003154A Expired - Lifetime KR100810012B1 (ko) | 2003-09-10 | 2004-08-30 | 격자 부정합 에피택셜 확장부와 소스 및 드레인 영역을갖는 변형 채널 cmos 트랜지스터의 구조 및 그 제조방법 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US6906360B2 (https=) |
| EP (1) | EP1668672A4 (https=) |
| JP (1) | JP4808622B2 (https=) |
| KR (1) | KR100810012B1 (https=) |
| CN (1) | CN1985375B (https=) |
| TW (1) | TWI318435B (https=) |
| WO (1) | WO2005027192A2 (https=) |
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| DE10351008B4 (de) * | 2003-10-31 | 2008-07-10 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung von Transistoren mit erhöhten Drain- und Sourcegebieten mit unterschiedlicher Höhe sowie ein Halbleiterbauelement |
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| JP2003188274A (ja) * | 2001-12-19 | 2003-07-04 | Toshiba Corp | 半導体装置及びその製造方法 |
| FR2834575B1 (fr) * | 2002-01-09 | 2004-07-09 | St Microelectronics Sa | Procede de modelisation et de realisation d'un circuit integre comportant au moins un transistor a effet de champ a grille isolee, et circuit integre correspondant |
| US20030166323A1 (en) * | 2002-03-01 | 2003-09-04 | Infineon Technologies North America Corp. | Raised extension structure for high performance cmos |
| US20040262683A1 (en) * | 2003-06-27 | 2004-12-30 | Bohr Mark T. | PMOS transistor strain optimization with raised junction regions |
| US6891192B2 (en) * | 2003-08-04 | 2005-05-10 | International Business Machines Corporation | Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions |
-
2003
- 2003-09-10 US US10/605,134 patent/US6906360B2/en not_active Expired - Lifetime
-
2004
- 2004-08-30 EP EP04782603A patent/EP1668672A4/en not_active Withdrawn
- 2004-08-30 KR KR1020067003154A patent/KR100810012B1/ko not_active Expired - Lifetime
- 2004-08-30 CN CN2004800259557A patent/CN1985375B/zh not_active Expired - Lifetime
- 2004-08-30 WO PCT/US2004/028163 patent/WO2005027192A2/en not_active Ceased
- 2004-08-30 JP JP2006526140A patent/JP4808622B2/ja not_active Expired - Fee Related
- 2004-09-01 TW TW093126405A patent/TWI318435B/zh not_active IP Right Cessation
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2005
- 2005-02-07 US US11/052,675 patent/US7297583B2/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5268324A (en) | 1992-05-27 | 1993-12-07 | International Business Machines Corporation | Modified silicon CMOS process having selectively deposited Si/SiGe FETS |
| US5583059A (en) | 1994-06-01 | 1996-12-10 | International Business Machines Corporation | Fabrication of vertical SiGe base HBT with lateral collector contact on thin SOI |
| US6358806B1 (en) | 2001-06-29 | 2002-03-19 | Lsi Logic Corporation | Silicon carbide CMOS channel |
| US20040175872A1 (en) * | 2003-03-07 | 2004-09-09 | Taiwan Semiconductor Manufacturing Company | Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1668672A4 (en) | 2008-06-25 |
| KR20060060691A (ko) | 2006-06-05 |
| WO2005027192A3 (en) | 2006-12-21 |
| EP1668672A2 (en) | 2006-06-14 |
| JP4808622B2 (ja) | 2011-11-02 |
| US6906360B2 (en) | 2005-06-14 |
| TWI318435B (en) | 2009-12-11 |
| CN1985375B (zh) | 2011-01-19 |
| CN1985375A (zh) | 2007-06-20 |
| TW200524087A (en) | 2005-07-16 |
| JP2007509486A (ja) | 2007-04-12 |
| US20050148133A1 (en) | 2005-07-07 |
| US20050051851A1 (en) | 2005-03-10 |
| US7297583B2 (en) | 2007-11-20 |
| WO2005027192A2 (en) | 2005-03-24 |
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