CN101969030B - 场效应晶体管 - Google Patents

场效应晶体管 Download PDF

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CN101969030B
CN101969030B CN2010102780048A CN201010278004A CN101969030B CN 101969030 B CN101969030 B CN 101969030B CN 2010102780048 A CN2010102780048 A CN 2010102780048A CN 201010278004 A CN201010278004 A CN 201010278004A CN 101969030 B CN101969030 B CN 101969030B
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gate stack
effect transistor
silicon
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CN101969030A (zh
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陈华杰
杜雷斯蒂·奇达姆巴拉奥
吴尚贤
斯德哈萨·潘达
沃纳·A·劳施
佐藤力
亨利·K·尤托莫
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Toshiba Electronic Devices and Storage Corp
International Business Machines Corp
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International Business Machines Corp
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Abstract

本发明涉及一种场效应晶体管FET(10)，其包括栅极叠层(29)，一对设置在所述栅极叠层(29)的侧壁上的第一隔离体(32)以及一对设置在所述栅极叠层(29)的相对两侧并与栅极叠层相隔第一距离的单晶半导体合金区(39)。所述FET(10)的源区和漏区(24)至少部分设置在所述半导体合金区(39)中，并由所述第一隔离体(32)对中的相应隔离体与所述栅极叠层(29)间隔开第二距离，所述第二距离可以不同于所述第一距离。

Description

场效应晶体管
本申请是申请日为2005年9月29日、国际申请号为PCT/US2005/034948、国家申请号为200580032811.9、发明名称为“使用牺牲隔离体的应变沟道FET”的专利申请的分案申请。
技术领域
本发明涉及半导体集成电路的制造，尤其涉及制造通过与沟道区相邻地设置半导体合金材料来对沟道区施加应力的应变沟道场效应晶体管(FET)，比如绝缘栅场效应晶体管(IGFET)的方法和装置。
背景技术
理论研究和经验均表明，如果对晶体管的沟道区施加足够大的应力来在其中产生应变，可以极大地提高晶体管中的载流子迁移率。应力被定义为单位面积的力。应变是一个无量纲量，被定义为当在某个方向(在这个例子中是物品的长度方向)施加力时，物品在同一方向的尺度相对于原始尺度的变化，例如长度相对于原始长度的变化。因此，应变可以是张性的或者压性的。在p型场效应晶体管(PFET)中，在沟道区的长度方向施加到沟道区的压应力，也就是纵向压应力，产生公知可以提高PFET的驱动电流的应变。
共同受让的同时待审美国专利申请No.10/604607(2003年8月4日递交)以及美国专利申请No.10/605134(2003年9月10日递交)描述了向FET的沟道区施加应力以提高其驱动电流的方法。这些申请在此通过引用完全被结合到本申请中。如其所述，向FET的沟道区施加应力的一种方式是形成与沟道区相邻的半导体合金材料的浅区，所述半导体合金材料与存在于沟道区中的半导体材料之间晶格失配。这样，在一个例子中，在沟道区(形成在硅的一个区域中)的相对两侧形成单晶硅锗(SiGe)的浅区。在结合到本申请中的所述申请中还描述了在衬底的与形成FET的源区和漏区的注入相一致的区域中设置SiGe区。
但是，并不总是希望应变沟道晶体管结构的SiGe区与源极和漏极注入的位置一致。尽管SiGe区需要靠近沟道区布置以施加所需的应力来获得高驱动电流，但是，如果将其布置得太靠近则会产生问题，比如，使得晶体管的阈值电压偏离所希望的值。
另外，希望将FET的源区和漏区相互靠近，以通过使沟道区的长度(L)较小来提高FET的驱动电流iD。这遵从下面的公式：
iD＝f(W/L)
其中iD是晶体管的驱动电流，W是宽度，L是沟道区长度，也就是衬底的源区和漏区之间的间隔。但是，对于源区和漏区可以设置得相互有多靠近是有限制的。如果设置得相互太靠近，则会发生短沟道效应，这会导致晶体管难以关断。如果晶体管不能完全关断，则当晶体管关断时会产生过大的泄漏电流，则导致即使在晶体管关断时也消耗更多的电能。过大的泄漏电流有时还会导致输出信号电平发生不希望有的漂移。
由于上述原因，希望提供一种结构和形成FET的方法，其中，半导体合金区形成得与沟道区之间有间隔，该间隔的选择与源区和漏区的边缘所在的位置无关。
发明内容
根据本发明的一个方面，提供了一种场效应晶体管(FET)，其包括上覆盖衬底的单晶半导体区的栅极叠层、一对设置在所述栅极叠层的侧壁上的第一隔离体，以及一对主要由设置在所述栅极叠层的相对两侧的单晶半导体合金组成的区域。所述半导体合金区中的每一个与所述栅极叠层相隔第一距离。FET的源区和漏区至少部分设置在半导体合金区中的相应一个中，使得源区和漏区分别由所述第一隔离体对中的第一隔离体与栅极叠层间隔开第二距离，所述第二距离不同于所述第一距离。
根据本发明的另一方面，提供了一种制造场效应晶体管(FET)的方法，包括：将上覆盖衬底的单晶半导体区域的栅极多晶半导体层图案化，以形成栅极多晶导体(PC，polyconductor)。之后，形成牺牲隔离体，上覆盖PC的侧壁，使所述单晶半导体区的在与牺牲隔离体相邻的位置的部分凹陷。之后，在所述位置外延生长主要由单晶半导体合金组成的区域，使得所述牺牲隔离体至少部分地确定所述单晶半导体合金区和所述PC之间的第一间隔。之后去除所述牺牲隔离体，然后完成所述FET。
附图说明
图1的剖面图图解了根据本发明的一种实施方式的应变沟道场效应晶体管；
图2到图11图解了根据本发明的一种实施方式，制造图1所示的应变沟道场效应晶体管的各个阶段。
具体实施方式
在图1中以剖面图的形式图解了根据本发明的一种实施方式的应变沟道场效应晶体管(FET)。FET 10或者是具有p型导电类型的沟道区22的PFET，或者是具有n型导电类型的NFET。沟道区22设置在FET的栅极导体29的下方。当FET10是PFET时，半导体合金区39设置得靠近沟道区并向沟道区22施加纵向压应力。优选地，沟道区22设置在主要由硅组成的区域14以及主要由硅锗组成的半导体合金区中。此后，将半导体合金区39称为硅锗区39。硅锗区39与栅极导体29之间的间隔最好是10nm或者更小，以便硅锗区39向沟道区22施加具有所需幅度的应力。如上所述，这样的应力提高PFET的驱动电流，使得PFET的开关速度更类似于没有应力施加到沟道区的NFET的开关速度。但是，与PFET的情况不一样，压应力会降低NFET的驱动电流。因此，如果FET是NFET并且硅锗区39是施加纵向压应力的类型，则要么应当省略硅锗区39，要么应将其设置得与PFET的情况相比更加远离沟道区22，以避免严重影响NFET的驱动电流。在被结合到本申请中的申请中，描述了在一个衬底上同时制造具有应变沟道的PFET和NFET的方法。在下面的说明中，针对的是PFET 10的制造，前提是如在所结合的申请中所描述的那样，进行必要的修改以形成NFET。
见图1，在一种优选的实施方式中，PFET 10的沟道区22设置在衬底17的相对较薄的绝缘体上单晶半导体(SOI)层14中，所述衬底17具有隐埋氧化物(BOX，buried oxide)层18将所述SOI层14与衬底的体区16隔开。或者，衬底17可以是体衬底，在这种情况下，省略BOX层18，这样的PFET具有靠近这样的体衬底的顶面设置的沟道区。当在SOI衬底中形成场效应晶体管(FET)时，常常比在体衬底中形成FET时实现更快的开关操作，因为在SOI的情况下，消除了晶体管的沟道区22和衬底的体区16之间的结电容。
按照下面的进一步描述，提供了一种制造FET比如PFET 10的方法，该PFET 10具有设置在单晶区14内的沟道区22，该单晶区14主要由第一半导体比如硅组成。当第一半导体是硅时，PFET 10包括主要由具有与硅不匹配的晶格常数的第二半导体材料比如硅锗组成的半导体合金区39。同样，半导体合金区39在下面称为硅锗区39。在一个例子中，硅锗(SixGey)区由化学式限定，其中x和y分别是Si和Ge的重量百分比，x加y等于百分之百。x和y之间的变化范围可以相当大，例如y的变化可以从1％到99％，在这种情况下，x对应的变化范围在99％到1％之间。在一种优选的实施方式中，PFET 10具有设置在SOI层14中的沟道区。在这样的实施方式中，SOI层14主要由基本上没有Ge含量的单晶硅组成，硅锗区39的锗含量的范围在组合的合金的重量的大约10％到大约50％之间。
但是，本发明不限于制造沟道区设置在纯硅晶体中的晶体管。衬底的单晶SOI区14可以主要由硅锗组成，硅锗的比例按照第一化学式Six1Gey1，其中，x1和y1是百分数，x1+y1＝100％，第二半导体的区域39主要由硅锗组成，硅锗具有根据第二化学式Six2Gey2的不同的比例，其中，x2和y2是百分数，x2+y2＝100％，x1不等于x2，y1不等于y2。在根据本发明的一种优选实施方式的方法中，通过与PFET10的沟道区22相邻的外延生长来形成与第一半导体晶格失配的第二半导体。
应当理解，本发明的教导也适用于其它类型的半导体中晶体管的制造。所述其它类型的半导体比如是组成为AlAInBGaCAsDPENF的III-V化合物半导体，其中，A，B，C，D，E，F分别代表每一种元素Al、In、Ga、As、P和N在半导体晶体中的百分比，这些百分比的和为百分之百。砷化镓(GaAs)、磷化铟(InP)、氮化镓(GaN)以及InGaAsP是这样的半导体的常见的例子。或者，本发明的教导也适用于II-VI化合物半导体区中晶体管的制造。
在图1中还图示了PFET 10的沟道区22设置在栅极导体29的下方，优选地具有与栅极电介质27接触的重掺杂多晶硅的下层26。栅极电介质27最好由在单晶半导体区14上热生长的二氧化硅层组成。或者，所述栅极电介质可以是任何适合的薄电介质材料，比如氮化硅，或者公知为高介电常数或者高k电介质材料的这种材料。在一种实施方式中，晕圈区(halo region)23和扩展区(extension region)25在沟道区22附近设置得与源区和漏区24相邻。但是，在某些实施方式中，不提供晕圈区23和扩展区25，晕圈区23和扩展区25是根据PFET10的具体设计要求提供的可选的特征。
栅极导体29的多晶硅下层26被重掺杂至大约1017cm-3到大约1021cm-3之间的浓度，举例来说大约为1019cm-3左右。优选地，PFET 10的多晶硅层26包括p型掺杂剂比如硼，以在PFET在操作中导通时与沟道区22的反型层(inversion layer)的p型导电类型的功函数匹配。栅极导体29优选地还包括设置在多晶硅部分26上方的低电阻部分28。该低电阻部分28比多晶硅部分26的电阻低得多，优选地包括金属、金属硅化物或者二者都包括。在一种优选的实施方式中，该低电阻部分28包括由自对准工艺形成的硅化物(自对准硅化物，salicide)，是任何合适的金属(包括但不限于钴、钼)的硅化物，镍、铌、钯、铂、钽、钛、钨和钒的单硅化物(monosilicide)。更为优选地，所述硅化物包括硅化钴、硅化钽、硅化钛、硅化钨和/或单硅化镍(nickel monosilicide)。
或者，所述栅极导体可以包括金属层(未图示)来取代与栅极电介质27接触的多晶硅层26，其也可以取代上覆的低电阻层。该金属层优选地已经被形成为在完成晶体管的源区和漏区的高温处理之后的替代栅极(replacement gate).
PFET 10的源区和漏区24至少部分地设置在硅锗区39中，源区和漏区24中的每一个由第一电介质隔离体32和设置在栅极导体29侧壁上的氧化物区31与PFET 10的栅极导体29横向隔开。这样，源区和漏区设置得处于与沟道区22的间隔有利地较小的位置，该间隔大约为5nm到15nm，在一种实施方式中为10nm。这样的间隔有利地与硅锗区到沟道区22的间隔一致。但是，源区和漏区与栅极导体之间的间隔可以不同于硅锗合金区与栅极导体之间的间隔。
作为例子，氧化物区31是通过最初填充氧化物区31之间的空间的多晶硅材料的氧化而形成的薄的热氧化物。在图1所示的实施方式中，在栅极导体29每一侧上的低电阻层40由第二电介质隔离体34与源区和漏区24间隔开。所述低电阻层最好是从淀积在硅锗层39上的金属以自对准方式形成的硅化物，即自对准硅化物，之后与硅锗反应以形成硅化物。所述硅化物可以是任何合适的金属(包括但不限于钴、钼)的化合物，镍、铌、钯、铂、钽、钛、钨和钒的单硅化物。更为优选地，所述硅化物包括硅化钴、硅化钽、硅化钛、硅化钨和/或单硅化镍。
图2到图11的横剖面图图解了根据本发明的一种优选的实施方式的绝缘栅应变沟道场效应晶体管(FET)的制造的各个阶段。与这里所引用的所有附图一样，图2所示的特征不是按比例绘制的。图2图解了制造的初始阶段，即提供用以制造FET的绝缘体上硅(SOI)衬底。如图2所示，SOI衬底17包括相对较薄的绝缘体上硅(SOI)层14以及由隐埋氧化物(BOX)层18与SOI层14分开的体区16。
图3图解了在SOI衬底17上已经形成了叠层的制造阶段。所述叠层包括(按从SOI层14向上的顺序)：栅极电介质27、多晶硅层26以及按顺序为氧化物42、氮化物44和氧化物46的上覆于多晶硅层26的各层。栅极电介质27包括比如如上所述的材料，例如通过绝缘体上硅层14的热氧化或者热氮化而形成。或者，通过淀积，尤其是通过低压化学蒸汽淀积(LPCVD)来形成栅极电介质27。通过淀积还可以形成其它类型的电介质来取代二氧化硅或者氮化硅，比如从若干种公知类别的高介电常数材料(也称为高k电介质材料)中的任何一种类别选择的电介质。
具体如图3所示，氧化物层46用作图案化的硬掩模层，用于对下伏于氧化物层46的各层进行图案化。这样的硬掩模层优选地由从四乙基原硅酸盐(TEOS)前体淀积的层提供，或者由硼磷硅酸盐(borophosphosilicate)玻璃(BPSG)或者未掺杂硅酸盐玻璃(USG)提供。在此制造阶段，多晶硅层26优选地为未掺杂的或者轻掺杂的，并在稍后的制造阶段例如通过离子注入被掺杂到优选的重掺杂剂浓度。
图4图解了在从叠层图案化了栅极叠层之后的随后的制造阶段。如图4所示，现在，栅极多晶硅层26、栅极盖层氧化物(gate cap oxide)42和栅极盖层氮化物(gate cap nitride)44留下，作为栅极电介质27上的图案化栅极叠层，栅极电介质27又上覆在衬底17上。另外，通过图案化暴露栅极多晶硅层26的侧壁，其然后比如通过热氧化被氧化，形成氧化物区31。
之后，如图5所示，在上覆多晶硅层26的侧壁的氧化物区31上形成一对牺牲隔离体50。所述隔离体50优选由相对于二氧化硅具有良好的蚀刻选择性的电介质材料例如氮化硅形成。
之后，如图6所示，对SOI层14的区域65执行垂直导入离子注入(vertically directed ion implant)58，以帮助限定后将要形成的硅锗区的底缘60的深度以及横向尺度62。该离子注入具有改变在区域65中的被注入的单晶硅材料，以允许其中的材料相对于SOI层14的其它区域被优先蚀刻的功能。这样的离子注入例如通过以足够的能量按剂量注入锗(Ge)离子来进行，以将其中的单晶硅材料“预先无定形化”(pre-amorphize)。如今通常使用的SOI衬底中的SOI层14比较薄，例如小于100nm，更为常见的是厚度在大约40nm和70nm之间。优选地，离子注入扩展到靠近BOX层18的顶面的深度60，以使稍后形成的硅锗区在那些区域65基本上取代SOI层14。期望的是，离子注入从SOI层14的顶面(由栅极电介质27限定)算起的深度60为BOX层18的顶面64的深度的80％或者更大。在一种实施方式中，当SOI层14的厚度为大约40nm时，区域65最好被注入到30nm或者更大的深度。与SOI层14具有相同或者类似厚度的单晶SiGe区对相邻的硅区产生压应力。这样的由在深度60的SiGe区施加的应力高于SiGe区比SOI层14薄很多时所能实现的应力，这是由于应力分布到更大面积的硅上。
见图7，执行一种工艺，相对于SOI层14的单晶硅材料选择性地优先蚀刻SOI层14的被注入的区域。该工艺导致产生具有深度60和横向尺度62的开口区66，其总体上与预先无定形化的区域65(图6)的深度和横向尺度一致。用反应离子蚀刻(RIE)工艺、相对于没有预先无定形化的层14的单晶硅材料有选择性的各向同性蚀刻或者二者的组合进行这样的蚀刻工艺。例如，在一种实施方式中，执行RIE工艺，接着进行为了“清洁”的目的的各向同性蚀刻，以去除层14的在RIE工艺之后留下的受损区域。这样的为了清洁目的的蚀刻可以是两步骤工艺的一部分，在所述两步骤工艺中，首先氧化暴露的表面68(例如用热氧化)，然后去除氧化物(例如各向同性蚀刻)。在另一种实施方式中，进行RIE工艺，接着对剩余的硅层14进行短时间的各向同性蚀刻，形成开口区66，其总体上与预先无定形化的区域(图6)一致。在另一种实施方式中，可以在这样的条件下进行各向同性蚀刻，以底切(undercut)下伏于部分隔离体50之下的半导体材料。另外还参考图1，每一个隔离体50被这样的蚀刻底切的横向距离是另一个可用来控制SiGe区39与FET 10的沟道区22的接近程度的参数。
之后，如图8所示，在单晶硅的顶面68上选择性地外延生长单晶硅锗(SiGe)层，以形成硅锗区39。在此选择性生长工艺中，在被隔离体50、氧化物盖层42和氮化物盖层44覆盖的区域不生长或者淀积SiGe材料。在一种SOI层14包括具有一定锗(Ge)含量的SiGe的实施方式中，此时生长的SiGe区39比SOI层14具有实质上更高百分比的锗。作为影响要施加到FET的沟道区的应力的参数，根据区域39到栅极多晶硅26的边缘的接近程度、区域39的厚度以及SOI层14的Ge含量(如果有的话)，选择区域39的Ge百分比含量。
此时，牺牲隔离体50已经履行了其隔离SiGe区39与栅极多晶硅26的功能，然后被从结构中去除。例如通过对隔离体50的氮化硅材料进行相对于氧化物以及硅和SiGe有选择性的各向同性蚀刻来去除隔离体50。隔离体50的去除还导致氮化物盖层44的去除，留下氧化物盖层42和侧壁氧化物区31在栅极多晶硅层26上方，如图9所示。
见图10，在去除牺牲隔离体后，使用栅极多晶硅26和氧化物区31作为掩模执行注入，以形成与沟道区22相邻的扩展区25和晕圈区23。该工艺导致SiGe区39被注入到如图10所示的深度70。在形成硅锗区之后形成晕圈区和扩展区是有益的，如下所述。硅锗区最好形成在掺杂剂浓度在空间上均匀的单晶半导体例如单晶硅的表面上。当注入晕圈区和扩展区时，形成垂直方向不均匀的掺杂剂分布。不希望在具有非均匀掺杂剂分布的表面上进行硅锗的外延生长，因为非均匀的掺杂剂分布会导致晶格在硅锗与硅晶体相遇的位置产生缺陷。这样的缺陷会使要由硅锗区施加到晶体管沟道区的应力的特性变差。根据本发明的该实施方式，可以通过以下方式避免上述问题：通过使用牺牲隔离体在包括硅区的侧壁30的表面上生长硅锗区，去除隔离体，之后执行晕圈注入和扩展注入。
之后，见图11，在结构的侧壁上，在侧壁氧化物区31上形成新的一对隔离体32。在一种实施方式中，所述新的隔离体32由氮化硅形成，以允许通过相对于氧化物盖层42的氧化物材料以及结构的硅和SiGe材料具有选择性的RIE工艺形成隔离体。但是，在形成隔离体32时可以使用能够相对于二氧化硅和其它硅氧化物、硅和SiGe被选择性蚀刻的任何电介质材料，例如其它非导电氮化物。使用栅极多晶硅26、氧化物区31和隔离体32作为掩模，进行另外的注入72以形成FET的源区和漏区24。该注入还具有将SiGe区39注入到一个深度74的效应，该深度可以与所述晕圈注入和/或扩展注入所到达的深度70(图10)相同或者不同。在一种实施方式中，用比用来形成晕圈和扩展区的注入大一个或者多个数量级的剂量进行源区和漏区注入72。由于源区和漏区24与栅极多晶硅26的间隔是由隔离体32限定的，硅锗区39与栅极多晶硅26的间隔是由牺牲隔离体50(图6)限定的，显然，使用本发明的该实施方式可以独立地控制所述间隔。这样，尽管源区和漏区24与栅极多晶硅26的具体间隔最好接近硅锗区39的间隔，但是源区和漏区24与栅极多晶硅可以间隔得近一些，或者远一些。
回到图1，进行处理以完成FET 10。如图中所示，在第一隔离体32的侧壁上形成附加隔离体34，附加隔离体34由电介质材料比如氮化物，尤其是氮化硅组成，可以以相比较而言比氧化物、硅和SiGe快得多的速度被蚀刻。之后，例如使用相对于氮化硅有选择性的蚀刻工艺，去除覆盖栅极多晶硅层26的顶面的氧化物盖层42(图11)。然后淀积金属，其经过与多晶硅和SiGe的反应而形成硅化物。硅化物形成金属(形成硅化物的金属)可以是下述金属中的一种或者多种，所述金属包括但不限于：钴、钼，镍、铌、钯、铂、钽、钛、钨和钒的单硅化物。更为优选地，该步骤形成的硅化物是硅化钴、硅化钽、硅化钛、硅化钨或者单硅化镍。
然后加热衬底17以加速反应，形成上覆盖SiGe区39的硅化物40和上覆盖栅极多晶硅层26的栅极硅化物层28。这样的硅化物(只在金属接触硅和SiGe的区域中形成)众所周知为自对准硅化物或者称salicide。在这个例子中，硅化物40和28与介于栅极多晶硅26和SiGe区39之间的隔离体32、34自对准。在隔离体32之后形成的隔离体34用来与SiGe区到栅极多晶硅26的间隔无关地控制硅化物区40的间隔。厚度可以与隔离体32无关地进行调节的隔离体34允许独立地控制硅化物区40和栅极多晶硅26之间的间隔。
这样，本发明提供了一种结构和一种方法，通过该方法，在FET的半导体合金区39之后形成晕圈区23和扩展区25的位置，并且所述位置的控制独立于源区和漏区24的位置。这样，本发明提供了一种改进的方法和结构，用于控制具有应变沟道区的FET的制造。
上面结合本发明的特定的优选实施方式对本发明进行了描述，但是本领域的普通技术人员应当理解可以在不脱离本发明的仅由所附权利要求限定的实质范围的前体下进行许多修改和改进。例如，在初始的图案化栅极叠层(图4)中，可以在多晶硅层26的侧壁上淀积氮化物区取代氧化物区31，并且可以使用氮化物盖层取代上覆盖多晶硅层26的氧化物盖层42。在这种情况下，隔离体50可以由氧化物而不是氮化物形成，然后可以选择用来去除隔离体50的工艺，使得相对于氮化物选择性蚀刻氧化物。
工业实用性
本发明的结构和方法可用于半导体集成电路的制造，提供一种成本经济的方法来制造通过相邻于沟道区设置的半导体合金材料向沟道区施加应力的应变沟道场效应晶体管(FET)比如绝缘栅场效应晶体管(IGFET)。

Claims (14)

1.一种场效应晶体管(10)，包括：
上覆盖衬底(17)的单晶半导体区(14)的栅极叠层(29)，所述单晶半导体区(14)具有第一组成；
一对设置在所述栅极叠层(29)的相对侧壁上的第一隔离体(32)；
一对由具有不同于所述第一组成的第二组成的单晶半导体合金组成的半导体合金区(39)，所述半导体合金区(39)设置在所述栅极叠层(29)的相对侧，每一个所述半导体合金区(39)与所述栅极叠层(29)相隔第一距离；以及
分别至少部分设置在所述半导体合金区(39)中的相应一个中的一对源区和漏区(24)，所述源区和所述漏区(24)分别通过所述第一隔离体(32)对中的相应一个与所述栅极叠层(29)间隔开第二距离，所述第二距离不同于所述第一距离，
其中，所述衬底(17)是绝缘体上硅衬底，所述单晶半导体区(14)是设置在所述绝缘体上硅衬底(17)的隐埋氧化物层(18)的上方的单晶硅区，
所述半导体合金区(39)的底缘(60)距所述单晶硅区(14)的顶面的深度为所述隐埋氧化物层(18)的顶部(64)距所述单晶硅区(14)的顶面的深度的80％或者更大。
2.如权利要求1所述的场效应晶体管，其中，所述第二距离比所述第一距离长。
3.如权利要求1所述的场效应晶体管，其中，所述半导体合金区(39)由硅锗组成。
4.如权利要求1所述的场效应晶体管，其中，所述半导体合金区(39)至少部分设置在设置于所述单晶半导体区(14)中的沟槽中。
5.如权利要求1所述的场效应晶体管，其中，所述底缘(60)的所述深度为所述隐埋氧化物层(18)的所述顶部(64)的所述深度的90％。
6.如权利要求1所述的场效应晶体管，还包括下伏于所述第一隔离体(32)并且至少部分下伏于所述栅极叠层(29)的扩展区(25)。
7.如权利要求6所述的场效应晶体管，还包括下伏于所述第一隔离体(32)并且至少部分下伏于所述栅极叠层(29)的晕圈区(23)。
8.如权利要求1所述的场效应晶体管，其中，所述栅极叠层(29)的所述侧壁被氧化，其中，所述第一隔离体(32)设置在被氧化的侧壁(31)上。
9.如权利要求1所述的场效应晶体管，还包括从所述第一隔离体(32)向外横向设置的第二隔离体(34)。
10.如权利要求9所述的场效应晶体管，还包括上覆盖所述半导体合金区(39)的硅化物区(40)，所述硅化物区(40)通过所述第一隔离体(32)和所述第二隔离体(34)与所述栅极叠层(29)隔开。
11.如权利要求1所述的场效应晶体管，其中，所述栅极叠层(29)包括栅极硅化物区(28)和多晶半导体区(26)，所述栅极硅化物区(28)上覆盖所述多晶半导体区(26)并与所述多晶半导体区(26)自对准。
12.如权利要求1所述的场效应晶体管，其中，所述第二距离小于所述第一距离。
13.如权利要求1所述的场效应晶体管，其中，所述单晶半导体合金包含至少两种半导体材料。
14.一种场效应晶体管(10)，包括：
上覆盖绝缘体上硅衬底(17)的单晶硅区(14)的栅极叠层(29)；
一对设置在所述栅极叠层(29)的相对侧壁上的第一隔离体(32)；
一对由单晶硅锗组成的设置在所述栅极叠层(29)的相对侧的硅锗区(39)，每一个所述硅锗区(39)与所述栅极叠层(29)相隔第一距离；
分别至少部分设置在所述硅锗区(39)中的相应一个中的一对源区和漏区(24)，所述源区和所述漏区(24)分别通过所述第一隔离体(32)对中的相应一个与所述栅极叠层(29)间隔开第二距离；以及
硅化物区，所述硅化物区中的至少一个(28)被设置为所述栅极叠层(29)的层，并且所述硅化物区中的至少另一个(40)至少部分上覆盖所述硅锗区(39)，
其中，所述衬底(17)是绝缘体上硅衬底，所述单晶硅区(14)是设置在所述绝缘体上硅衬底(17)的隐埋氧化物层(18)的上方的单晶硅区，
所述硅锗区(39)的底缘(60)距所述单晶硅区(14)的顶面的深度为所述隐埋氧化物层(18)的顶部(64)距所述单晶硅区(14)的顶面的深度的80％或者更大。
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