KR100727203B1 - 불휘발성 기억 장치 및 불휘발성 기억 장치의 데이터 기록방법 - Google Patents

불휘발성 기억 장치 및 불휘발성 기억 장치의 데이터 기록방법 Download PDF

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Publication number
KR100727203B1
KR100727203B1 KR1020050068942A KR20050068942A KR100727203B1 KR 100727203 B1 KR100727203 B1 KR 100727203B1 KR 1020050068942 A KR1020050068942 A KR 1020050068942A KR 20050068942 A KR20050068942 A KR 20050068942A KR 100727203 B1 KR100727203 B1 KR 100727203B1
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KR
South Korea
Prior art keywords
memory cell
control gate
line
cell block
selected memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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KR1020050068942A
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English (en)
Korean (ko)
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KR20060048864A (ko
Inventor
사토루 고다이라
히토시 고바야시
기미히로 마에무라
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세이코 엡슨 가부시키가이샤
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Publication of KR20060048864A publication Critical patent/KR20060048864A/ko
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Publication of KR100727203B1 publication Critical patent/KR100727203B1/ko
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • G11C16/12Programming voltage switching circuits
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/08Address circuits; Decoders; Word-line control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/24Bit-line control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
KR1020050068942A 2004-07-30 2005-07-28 불휘발성 기억 장치 및 불휘발성 기억 장치의 데이터 기록방법 Expired - Fee Related KR100727203B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2004-00224130 2004-07-30
JP2004224130A JP2006048749A (ja) 2004-07-30 2004-07-30 不揮発性記憶装置及び不揮発性記憶装置のデータ書き込み方法

Publications (2)

Publication Number Publication Date
KR20060048864A KR20060048864A (ko) 2006-05-18
KR100727203B1 true KR100727203B1 (ko) 2007-06-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050068942A Expired - Fee Related KR100727203B1 (ko) 2004-07-30 2005-07-28 불휘발성 기억 장치 및 불휘발성 기억 장치의 데이터 기록방법

Country Status (4)

Country Link
US (1) US7292475B2 (enExample)
JP (1) JP2006048749A (enExample)
KR (1) KR100727203B1 (enExample)
CN (1) CN100520970C (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4548603B2 (ja) 2005-06-08 2010-09-22 セイコーエプソン株式会社 半導体装置
JP4591691B2 (ja) * 2005-06-07 2010-12-01 セイコーエプソン株式会社 半導体装置
US7633828B2 (en) * 2006-07-31 2009-12-15 Sandisk 3D Llc Hierarchical bit line bias bus for block selectable memory array
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US8085588B2 (en) * 2009-04-30 2011-12-27 Spansion Llc Semiconductor device and control method thereof
KR101253443B1 (ko) * 2011-06-09 2013-04-11 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법
KR20130120858A (ko) 2012-04-26 2013-11-05 한국전자통신연구원 전달게이트가 삽입된 이이피롬 셀
KR101982141B1 (ko) 2013-01-04 2019-05-27 한국전자통신연구원 이이피롬 셀 및 이이피롬 장치
CN111508546B (zh) * 2019-01-31 2023-06-27 群联电子股份有限公司 解码方法、存储器控制电路单元与存储器存储装置
US10706936B1 (en) 2019-04-26 2020-07-07 Western Digital Technologies, Inc. System and method for avoiding back to back program failure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6044017A (en) * 1997-05-19 2000-03-28 Samsung Electronics, Co., Ltd. Flash memory device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3267974D1 (en) * 1982-03-17 1986-01-30 Itt Ind Gmbh Deutsche Electrically erasable memory matrix (eeprom)
DE3277715D1 (en) * 1982-08-06 1987-12-23 Itt Ind Gmbh Deutsche Electrically programmable memory array
FR2622038B1 (fr) * 1987-10-19 1990-01-19 Thomson Semiconducteurs Procede de programmation des cellules memoire d'une memoire et circuit pour la mise en oeuvre de ce procede
FR2623651B1 (fr) * 1987-11-20 1992-11-27 Sgs Thomson Microelectronics Plan memoire et procede et prototype de definition d'un circuit integre electronique comportant un tel plan memoire
JP2685966B2 (ja) * 1990-06-22 1997-12-08 株式会社東芝 不揮発性半導体記憶装置
US5471422A (en) 1994-04-11 1995-11-28 Motorola, Inc. EEPROM cell with isolation transistor and methods for making and operating the same
JPH08222649A (ja) 1995-02-17 1996-08-30 Sony Corp 半導体不揮発性記憶装置
US5914514A (en) 1996-09-27 1999-06-22 Xilinx, Inc. Two transistor flash EPROM cell
US6643174B2 (en) * 2001-12-20 2003-11-04 Winbond Electronics Corporation EEPROM cells and array with reduced write disturbance

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6044017A (en) * 1997-05-19 2000-03-28 Samsung Electronics, Co., Ltd. Flash memory device

Also Published As

Publication number Publication date
CN1747068A (zh) 2006-03-15
KR20060048864A (ko) 2006-05-18
CN100520970C (zh) 2009-07-29
US20060023509A1 (en) 2006-02-02
JP2006048749A (ja) 2006-02-16
US7292475B2 (en) 2007-11-06

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