CN100520970C - 非易失性存储装置以及非易失性存储装置的数据写入方法 - Google Patents
非易失性存储装置以及非易失性存储装置的数据写入方法 Download PDFInfo
- Publication number
- CN100520970C CN100520970C CNB2005100888803A CN200510088880A CN100520970C CN 100520970 C CN100520970 C CN 100520970C CN B2005100888803 A CNB2005100888803 A CN B2005100888803A CN 200510088880 A CN200510088880 A CN 200510088880A CN 100520970 C CN100520970 C CN 100520970C
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- China
- Prior art keywords
- control gate
- memory cell
- line
- cell block
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000003860 storage Methods 0.000 claims abstract description 169
- 210000004027 cell Anatomy 0.000 claims 81
- 210000000352 storage cell Anatomy 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 20
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- 201000001130 congenital generalized lipodystrophy type 1 Diseases 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 230000004913 activation Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
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Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004224130 | 2004-07-30 | ||
| JP2004224130A JP2006048749A (ja) | 2004-07-30 | 2004-07-30 | 不揮発性記憶装置及び不揮発性記憶装置のデータ書き込み方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1747068A CN1747068A (zh) | 2006-03-15 |
| CN100520970C true CN100520970C (zh) | 2009-07-29 |
Family
ID=35731975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100888803A Expired - Fee Related CN100520970C (zh) | 2004-07-30 | 2005-07-29 | 非易失性存储装置以及非易失性存储装置的数据写入方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7292475B2 (enExample) |
| JP (1) | JP2006048749A (enExample) |
| KR (1) | KR100727203B1 (enExample) |
| CN (1) | CN100520970C (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4548603B2 (ja) | 2005-06-08 | 2010-09-22 | セイコーエプソン株式会社 | 半導体装置 |
| JP4591691B2 (ja) * | 2005-06-07 | 2010-12-01 | セイコーエプソン株式会社 | 半導体装置 |
| US7633828B2 (en) * | 2006-07-31 | 2009-12-15 | Sandisk 3D Llc | Hierarchical bit line bias bus for block selectable memory array |
| US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
| US8085588B2 (en) * | 2009-04-30 | 2011-12-27 | Spansion Llc | Semiconductor device and control method thereof |
| KR101253443B1 (ko) * | 2011-06-09 | 2013-04-11 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그 동작 방법 |
| KR20130120858A (ko) | 2012-04-26 | 2013-11-05 | 한국전자통신연구원 | 전달게이트가 삽입된 이이피롬 셀 |
| KR101982141B1 (ko) | 2013-01-04 | 2019-05-27 | 한국전자통신연구원 | 이이피롬 셀 및 이이피롬 장치 |
| CN111508546B (zh) * | 2019-01-31 | 2023-06-27 | 群联电子股份有限公司 | 解码方法、存储器控制电路单元与存储器存储装置 |
| US10706936B1 (en) | 2019-04-26 | 2020-07-07 | Western Digital Technologies, Inc. | System and method for avoiding back to back program failure |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3267974D1 (en) * | 1982-03-17 | 1986-01-30 | Itt Ind Gmbh Deutsche | Electrically erasable memory matrix (eeprom) |
| DE3277715D1 (en) * | 1982-08-06 | 1987-12-23 | Itt Ind Gmbh Deutsche | Electrically programmable memory array |
| FR2622038B1 (fr) * | 1987-10-19 | 1990-01-19 | Thomson Semiconducteurs | Procede de programmation des cellules memoire d'une memoire et circuit pour la mise en oeuvre de ce procede |
| FR2623651B1 (fr) * | 1987-11-20 | 1992-11-27 | Sgs Thomson Microelectronics | Plan memoire et procede et prototype de definition d'un circuit integre electronique comportant un tel plan memoire |
| JP2685966B2 (ja) * | 1990-06-22 | 1997-12-08 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| US5471422A (en) | 1994-04-11 | 1995-11-28 | Motorola, Inc. | EEPROM cell with isolation transistor and methods for making and operating the same |
| JPH08222649A (ja) | 1995-02-17 | 1996-08-30 | Sony Corp | 半導体不揮発性記憶装置 |
| US5914514A (en) | 1996-09-27 | 1999-06-22 | Xilinx, Inc. | Two transistor flash EPROM cell |
| KR100252476B1 (ko) | 1997-05-19 | 2000-04-15 | 윤종용 | 플레이트 셀 구조의 전기적으로 소거 및 프로그램 가능한 셀들을 구비한 불 휘발성 반도체 메모리 장치및 그것의 프로그램 방법 |
| US6643174B2 (en) * | 2001-12-20 | 2003-11-04 | Winbond Electronics Corporation | EEPROM cells and array with reduced write disturbance |
-
2004
- 2004-07-30 JP JP2004224130A patent/JP2006048749A/ja active Pending
-
2005
- 2005-07-08 US US11/176,324 patent/US7292475B2/en not_active Expired - Fee Related
- 2005-07-28 KR KR1020050068942A patent/KR100727203B1/ko not_active Expired - Fee Related
- 2005-07-29 CN CNB2005100888803A patent/CN100520970C/zh not_active Expired - Fee Related
Non-Patent Citations (2)
| Title |
|---|
| A 16H E2PROM Employing new array architecture anddesigned-in reliability feature. Yaron.IEEE Journal of Solid-State Circuit,Vol.17 No.5. 1982 * |
| Hi-MNOS II technoogy for a 64-kbit byte-eraseable 5-V-onlyEEPROM. Yatsuda.IEEE Transactions of Electron Device,Vol.32 No.2. 1985 * |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100727203B1 (ko) | 2007-06-13 |
| CN1747068A (zh) | 2006-03-15 |
| KR20060048864A (ko) | 2006-05-18 |
| US20060023509A1 (en) | 2006-02-02 |
| JP2006048749A (ja) | 2006-02-16 |
| US7292475B2 (en) | 2007-11-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090729 Termination date: 20160729 |