KR100640639B1 - 미세콘택을 포함하는 반도체소자 및 그 제조방법 - Google Patents

미세콘택을 포함하는 반도체소자 및 그 제조방법 Download PDF

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Publication number
KR100640639B1
KR100640639B1 KR1020050032296A KR20050032296A KR100640639B1 KR 100640639 B1 KR100640639 B1 KR 100640639B1 KR 1020050032296 A KR1020050032296 A KR 1020050032296A KR 20050032296 A KR20050032296 A KR 20050032296A KR 100640639 B1 KR100640639 B1 KR 100640639B1
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South Korea
Prior art keywords
contact
interlayer insulating
contact hole
forming
spacer
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Expired - Fee Related
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KR1020050032296A
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English (en)
Korean (ko)
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KR20060110096A (ko
Inventor
이지영
강현재
우상균
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삼성전자주식회사
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Priority to KR1020050032296A priority Critical patent/KR100640639B1/ko
Priority to US11/367,436 priority patent/US7855408B2/en
Priority to JP2006104573A priority patent/JP5047529B2/ja
Publication of KR20060110096A publication Critical patent/KR20060110096A/ko
Application granted granted Critical
Publication of KR100640639B1 publication Critical patent/KR100640639B1/ko
Priority to US12/943,142 priority patent/US8242018B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
KR1020050032296A 2005-04-19 2005-04-19 미세콘택을 포함하는 반도체소자 및 그 제조방법 Expired - Fee Related KR100640639B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020050032296A KR100640639B1 (ko) 2005-04-19 2005-04-19 미세콘택을 포함하는 반도체소자 및 그 제조방법
US11/367,436 US7855408B2 (en) 2005-04-19 2006-03-06 Semiconductor device having fine contacts
JP2006104573A JP5047529B2 (ja) 2005-04-19 2006-04-05 微細コンタクトを備える半導体素子及びその製造方法
US12/943,142 US8242018B2 (en) 2005-04-19 2010-11-10 Semiconductor device having fine contacts and method of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050032296A KR100640639B1 (ko) 2005-04-19 2005-04-19 미세콘택을 포함하는 반도체소자 및 그 제조방법

Publications (2)

Publication Number Publication Date
KR20060110096A KR20060110096A (ko) 2006-10-24
KR100640639B1 true KR100640639B1 (ko) 2006-10-31

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KR1020050032296A Expired - Fee Related KR100640639B1 (ko) 2005-04-19 2005-04-19 미세콘택을 포함하는 반도체소자 및 그 제조방법

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US (2) US7855408B2 (enExample)
JP (1) JP5047529B2 (enExample)
KR (1) KR100640639B1 (enExample)

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US7666578B2 (en) 2006-09-14 2010-02-23 Micron Technology, Inc. Efficient pitch multiplication process
KR100789391B1 (ko) * 2006-10-20 2008-01-02 삼성전자주식회사 콘택 구조물 형성 방법
US8809932B2 (en) * 2007-03-26 2014-08-19 Samsung Electronics Co., Ltd. Semiconductor memory device, method of fabricating the same, and devices employing the semiconductor memory device
KR100924611B1 (ko) * 2007-05-11 2009-11-02 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성방법
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
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US8563229B2 (en) 2007-07-31 2013-10-22 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
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US7659208B2 (en) 2007-12-06 2010-02-09 Micron Technology, Inc Method for forming high density patterns
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Also Published As

Publication number Publication date
US20060231900A1 (en) 2006-10-19
US8242018B2 (en) 2012-08-14
US20110076846A1 (en) 2011-03-31
US7855408B2 (en) 2010-12-21
KR20060110096A (ko) 2006-10-24
JP2006303488A (ja) 2006-11-02
JP5047529B2 (ja) 2012-10-10

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