KR100541157B1 - 플래쉬 메모리 소자의 제조 방법 - Google Patents

플래쉬 메모리 소자의 제조 방법 Download PDF

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Publication number
KR100541157B1
KR100541157B1 KR1020040011753A KR20040011753A KR100541157B1 KR 100541157 B1 KR100541157 B1 KR 100541157B1 KR 1020040011753 A KR1020040011753 A KR 1020040011753A KR 20040011753 A KR20040011753 A KR 20040011753A KR 100541157 B1 KR100541157 B1 KR 100541157B1
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KR
South Korea
Prior art keywords
film
oxide film
polysilicon
forming
gas
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KR1020040011753A
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English (en)
Korean (ko)
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KR20050083280A (ko
Inventor
주광철
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020040011753A priority Critical patent/KR100541157B1/ko
Priority to JP2004191492A priority patent/JP4642390B2/ja
Priority to US10/883,402 priority patent/US7148109B2/en
Priority to TW093119254A priority patent/TWI268577B/zh
Publication of KR20050083280A publication Critical patent/KR20050083280A/ko
Application granted granted Critical
Publication of KR100541157B1 publication Critical patent/KR100541157B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/91—Controlling charging state at semiconductor-insulator interface

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
KR1020040011753A 2004-02-23 2004-02-23 플래쉬 메모리 소자의 제조 방법 KR100541157B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020040011753A KR100541157B1 (ko) 2004-02-23 2004-02-23 플래쉬 메모리 소자의 제조 방법
JP2004191492A JP4642390B2 (ja) 2004-02-23 2004-06-29 フラッシュメモリ素子の製造方法
US10/883,402 US7148109B2 (en) 2004-02-23 2004-06-30 Method for manufacturing flash memory device
TW093119254A TWI268577B (en) 2004-02-23 2004-06-30 Method for manufacturing flash memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040011753A KR100541157B1 (ko) 2004-02-23 2004-02-23 플래쉬 메모리 소자의 제조 방법

Publications (2)

Publication Number Publication Date
KR20050083280A KR20050083280A (ko) 2005-08-26
KR100541157B1 true KR100541157B1 (ko) 2006-01-10

Family

ID=34858796

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020040011753A KR100541157B1 (ko) 2004-02-23 2004-02-23 플래쉬 메모리 소자의 제조 방법

Country Status (4)

Country Link
US (1) US7148109B2 (ja)
JP (1) JP4642390B2 (ja)
KR (1) KR100541157B1 (ja)
TW (1) TWI268577B (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180067059A (ko) 2016-12-12 2018-06-20 연세대학교 산학협력단 산화물 박막, 이의 제조방법 및 이를 포함하는 산화물 박막 트랜지스터

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100673242B1 (ko) * 2005-06-24 2007-01-22 주식회사 하이닉스반도체 플래쉬 메모리 소자의 유전체막 제조방법
KR100763123B1 (ko) * 2005-12-12 2007-10-04 주식회사 하이닉스반도체 플래시 메모리 소자의 유전체막 형성 방법
KR100927751B1 (ko) * 2006-03-16 2009-11-20 주식회사 하이닉스반도체 플래시 메모리 소자의 제조방법
JP4921837B2 (ja) * 2006-04-14 2012-04-25 株式会社東芝 半導体装置の製造方法
KR100739988B1 (ko) * 2006-06-28 2007-07-16 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조방법
KR100815968B1 (ko) * 2007-05-17 2008-03-24 주식회사 동부하이텍 반도체 소자 제조 방법
CN101312188A (zh) * 2007-05-25 2008-11-26 东部高科股份有限公司 半导体装置及其制造方法
KR100860469B1 (ko) * 2007-06-26 2008-09-25 주식회사 동부하이텍 플래쉬 메모리 제조방법
US8089114B2 (en) 2007-11-08 2012-01-03 Samsung Electronics Co., Ltd. Non-volatile memory devices including blocking and interface patterns between charge storage patterns and control electrodes and related methods
US8791445B2 (en) * 2012-03-01 2014-07-29 Intermolecular, Inc. Interfacial oxide used as switching layer in a nonvolatile resistive memory element
KR102001228B1 (ko) 2012-07-12 2019-10-21 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN110534412A (zh) * 2019-09-09 2019-12-03 上海华虹宏力半导体制造有限公司 避免磷掺杂多晶硅缺陷的方法及存储器单元的制造方法
JP2022070034A (ja) * 2020-10-26 2022-05-12 株式会社Sumco 貼り合わせウェーハ用の支持基板の製造方法、および貼り合わせウェーハ用の支持基板

Family Cites Families (10)

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Publication number Priority date Publication date Assignee Title
JPS5442988A (en) * 1977-09-09 1979-04-05 Nec Corp Semiconductor device
JPS62247570A (ja) * 1986-06-06 1987-10-28 Nec Corp 不揮発性半導体記憶装置
JP3588497B2 (ja) * 1995-03-24 2004-11-10 株式会社ルネサステクノロジ 半導体装置の製造方法
JPH0955485A (ja) * 1995-08-14 1997-02-25 Sony Corp 半導体装置の製造方法
JPH10154761A (ja) * 1996-11-21 1998-06-09 Mitsubishi Electric Corp 不揮発性半導体記憶装置の製造方法
JPH10335500A (ja) * 1997-06-05 1998-12-18 Toshiba Microelectron Corp 半導体装置の製造方法
JPH11111871A (ja) * 1997-10-06 1999-04-23 Seiko Epson Corp 不揮発性半導体記憶装置及びその製造方法
US6187633B1 (en) * 1998-10-09 2001-02-13 Chartered Semiconductor Manufacturing, Ltd. Method of manufacturing a gate structure for a semiconductor memory device with improved breakdown voltage and leakage rate
US6551879B1 (en) * 2002-03-21 2003-04-22 Macronix International Co., Inc. Method for forming an oxide layer on a nitride layer
US6893920B2 (en) * 2002-09-12 2005-05-17 Promos Technologies, Inc. Method for forming a protective buffer layer for high temperature oxide processing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180067059A (ko) 2016-12-12 2018-06-20 연세대학교 산학협력단 산화물 박막, 이의 제조방법 및 이를 포함하는 산화물 박막 트랜지스터

Also Published As

Publication number Publication date
JP4642390B2 (ja) 2011-03-02
JP2005236247A (ja) 2005-09-02
TWI268577B (en) 2006-12-11
TW200529381A (en) 2005-09-01
US20050186736A1 (en) 2005-08-25
US7148109B2 (en) 2006-12-12
KR20050083280A (ko) 2005-08-26

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