KR100349094B1 - 집적반도체메모리용용장도회로 - Google Patents
집적반도체메모리용용장도회로 Download PDFInfo
- Publication number
- KR100349094B1 KR100349094B1 KR1019950024768A KR19950024768A KR100349094B1 KR 100349094 B1 KR100349094 B1 KR 100349094B1 KR 1019950024768 A KR1019950024768 A KR 1019950024768A KR 19950024768 A KR19950024768 A KR 19950024768A KR 100349094 B1 KR100349094 B1 KR 100349094B1
- Authority
- KR
- South Korea
- Prior art keywords
- address
- circuit
- fet
- partial
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/806—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout by reducing size of decoders
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/812—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a reduced amount of fuses
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP94112661.7 | 1994-08-12 | ||
| EP94112661A EP0697659B1 (de) | 1994-08-12 | 1994-08-12 | Redundanz-Schaltungsanordnung für einen integrierten Halbleiterspeicher |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960008534A KR960008534A (ko) | 1996-03-22 |
| KR100349094B1 true KR100349094B1 (ko) | 2002-12-28 |
Family
ID=8216199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950024768A Expired - Fee Related KR100349094B1 (ko) | 1994-08-12 | 1995-08-11 | 집적반도체메모리용용장도회로 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US5657279A (enExample) |
| EP (1) | EP0697659B1 (enExample) |
| JP (1) | JP3626254B2 (enExample) |
| KR (1) | KR100349094B1 (enExample) |
| AT (1) | ATE187826T1 (enExample) |
| DE (1) | DE59409008D1 (enExample) |
| TW (1) | TW273628B (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5706292A (en) | 1996-04-25 | 1998-01-06 | Micron Technology, Inc. | Layout for a semiconductor memory device having redundant elements |
| JP2982695B2 (ja) * | 1996-07-15 | 1999-11-29 | 日本電気株式会社 | 半導体メモリ |
| CA2202692C (en) * | 1997-04-14 | 2006-06-13 | Mosaid Technologies Incorporated | Column redundancy in semiconductor memories |
| US6002620A (en) * | 1998-01-09 | 1999-12-14 | Information Storage Devices, Inc. | Method and apparatus of column redundancy for non-volatile analog and multilevel memory |
| US6137735A (en) * | 1998-10-30 | 2000-10-24 | Mosaid Technologies Incorporated | Column redundancy circuit with reduced signal path delay |
| US6473872B1 (en) | 2000-03-08 | 2002-10-29 | Infineon Technologies Ag | Address decoding system and method for failure toleration in a memory bank |
| CN104835529B (zh) * | 2014-02-10 | 2018-05-29 | 晶豪科技股份有限公司 | 用于半导体装置的冗余评估电路 |
| CN113327641B (zh) * | 2020-02-28 | 2024-05-03 | 中芯国际集成电路制造(上海)有限公司 | eFuse存储单元、eFuse存储阵列及其使用方法、eFuse系统 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04103099A (ja) * | 1990-08-23 | 1992-04-06 | Toshiba Corp | 半導体記憶装置 |
| JPH0831279B2 (ja) * | 1990-12-20 | 1996-03-27 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 冗長システム |
| JP2629475B2 (ja) * | 1991-04-04 | 1997-07-09 | 松下電器産業株式会社 | 半導体集積回路 |
| US5293564A (en) * | 1991-04-30 | 1994-03-08 | Texas Instruments Incorporated | Address match scheme for DRAM redundancy scheme |
-
1994
- 1994-08-12 EP EP94112661A patent/EP0697659B1/de not_active Expired - Lifetime
- 1994-08-12 AT AT94112661T patent/ATE187826T1/de not_active IP Right Cessation
- 1994-08-12 DE DE59409008T patent/DE59409008D1/de not_active Expired - Lifetime
-
1995
- 1995-08-04 TW TW084108162A patent/TW273628B/zh active
- 1995-08-09 JP JP22472295A patent/JP3626254B2/ja not_active Expired - Fee Related
- 1995-08-11 KR KR1019950024768A patent/KR100349094B1/ko not_active Expired - Fee Related
- 1995-08-14 US US08/514,602 patent/US5657279A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| TW273628B (enExample) | 1996-04-01 |
| EP0697659B1 (de) | 1999-12-15 |
| JPH0896595A (ja) | 1996-04-12 |
| HK1004494A1 (en) | 1998-11-27 |
| KR960008534A (ko) | 1996-03-22 |
| ATE187826T1 (de) | 2000-01-15 |
| DE59409008D1 (de) | 2000-01-20 |
| EP0697659A1 (de) | 1996-02-21 |
| US5657279A (en) | 1997-08-12 |
| JP3626254B2 (ja) | 2005-03-02 |
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| JPH0250560B2 (enExample) | ||
| KR950001731B1 (ko) | 저전력퓨우즈박스 및 이를 구비하는 리던던시회로 | |
| KR970005122B1 (ko) | 반도체 소자의 리던던시 회로 |
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|---|---|---|---|
| PA0109 | Patent application |
St.27 status event code: A-0-1-A10-A12-nap-PA0109 |
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St.27 status event code: A-3-3-R10-R17-oth-X000 |
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| A201 | Request for examination | ||
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