KR100340395B1 - 반도체 장치 및 그 제조 방법 - Google Patents

반도체 장치 및 그 제조 방법 Download PDF

Info

Publication number
KR100340395B1
KR100340395B1 KR1020000051844A KR20000051844A KR100340395B1 KR 100340395 B1 KR100340395 B1 KR 100340395B1 KR 1020000051844 A KR1020000051844 A KR 1020000051844A KR 20000051844 A KR20000051844 A KR 20000051844A KR 100340395 B1 KR100340395 B1 KR 100340395B1
Authority
KR
South Korea
Prior art keywords
insulating film
gate electrode
soi substrate
device isolation
dtmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020000051844A
Other languages
English (en)
Korean (ko)
Other versions
KR20010030243A (ko
Inventor
히라노유우이찌
Original Assignee
다니구찌 이찌로오, 기타오카 다카시
미쓰비시덴키 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 다니구찌 이찌로오, 기타오카 다카시, 미쓰비시덴키 가부시키가이샤 filed Critical 다니구찌 이찌로오, 기타오카 다카시
Publication of KR20010030243A publication Critical patent/KR20010030243A/ko
Application granted granted Critical
Publication of KR100340395B1 publication Critical patent/KR100340395B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1020000051844A 1999-09-03 2000-09-02 반도체 장치 및 그 제조 방법 Expired - Fee Related KR100340395B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP25047599A JP2001077368A (ja) 1999-09-03 1999-09-03 半導体装置及びその製造方法
JP1999-250475 1999-09-03

Publications (2)

Publication Number Publication Date
KR20010030243A KR20010030243A (ko) 2001-04-16
KR100340395B1 true KR100340395B1 (ko) 2002-06-15

Family

ID=17208415

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000051844A Expired - Fee Related KR100340395B1 (ko) 1999-09-03 2000-09-02 반도체 장치 및 그 제조 방법

Country Status (4)

Country Link
US (2) US6252280B1 (enExample)
JP (1) JP2001077368A (enExample)
KR (1) KR100340395B1 (enExample)
DE (1) DE10043183A1 (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6444432B1 (en) * 1997-06-13 2002-09-03 Alan M. Kleinfeld Method of detection of cardiac ischemia using fatty acid binding protein
JP2000243967A (ja) * 1999-02-22 2000-09-08 Sony Corp 半導体装置の製造方法
JP3716406B2 (ja) * 2000-02-08 2005-11-16 富士通株式会社 絶縁ゲート型半導体装置及びその製造方法
JP4698793B2 (ja) * 2000-04-03 2011-06-08 ルネサスエレクトロニクス株式会社 半導体装置
JP4988086B2 (ja) * 2000-06-13 2012-08-01 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法並びに抵抗器及び半導体素子
JP2002033484A (ja) * 2000-07-18 2002-01-31 Mitsubishi Electric Corp 半導体装置
JP3990858B2 (ja) * 2000-07-31 2007-10-17 株式会社東芝 半導体装置
JP2002185011A (ja) * 2000-12-19 2002-06-28 Seiko Epson Corp 半導体装置
JP2002299633A (ja) * 2001-04-03 2002-10-11 Sony Corp 電界効果型トランジスタ
TW200305976A (en) 2001-04-03 2003-11-01 Matsushita Electric Industrial Co Ltd Semiconductor device and method for fabricating the same
JP2003318405A (ja) 2002-04-25 2003-11-07 Mitsubishi Electric Corp 半導体装置およびその製造方法
US7196369B2 (en) * 2002-07-15 2007-03-27 Macronix International Co., Ltd. Plasma damage protection circuit for a semiconductor device
JP4294935B2 (ja) 2002-10-17 2009-07-15 株式会社ルネサステクノロジ 半導体装置
JP4154578B2 (ja) * 2002-12-06 2008-09-24 日本電気株式会社 半導体装置及びその製造方法
US6905919B2 (en) 2003-07-29 2005-06-14 Chartered Semiconductor Manufacturing Ltd. Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension
JP2006049784A (ja) * 2003-08-28 2006-02-16 Renesas Technology Corp 半導体記憶装置及びその製造方法
TWI244729B (en) 2003-08-28 2005-12-01 Renesas Tech Corp Semiconductor memory device and method of manufacturing the same
JP2006054430A (ja) * 2004-07-12 2006-02-23 Renesas Technology Corp 半導体装置
KR100629264B1 (ko) 2004-07-23 2006-09-29 삼성전자주식회사 게이트 관통 바디 콘택을 갖는 반도체소자 및 그 제조방법
JP2006066691A (ja) * 2004-08-27 2006-03-09 Renesas Technology Corp 半導体装置およびその製造方法
US7170816B2 (en) * 2004-12-16 2007-01-30 Macronix International Co., Ltd. Method and apparatus for passing charge from word lines during manufacture
JP5270876B2 (ja) * 2007-08-22 2013-08-21 セイコーインスツル株式会社 半導体装置
US7964897B2 (en) * 2008-07-22 2011-06-21 Honeywell International Inc. Direct contact to area efficient body tie process flow
US8680617B2 (en) * 2009-10-06 2014-03-25 International Business Machines Corporation Split level shallow trench isolation for area efficient body contacts in SOI MOSFETS
US8558960B2 (en) 2010-09-13 2013-10-15 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and method for manufacturing the same
US9490249B2 (en) 2014-04-30 2016-11-08 Macronix International Co., Ltd. Antenna effect discharge circuit and manufacturing method
FR3069373A1 (fr) * 2017-07-19 2019-01-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Transistors double grilles optimises et procede de fabrication
US10546929B2 (en) 2017-07-19 2020-01-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Optimized double-gate transistors and fabricating process

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5559368A (en) * 1994-08-30 1996-09-24 The Regents Of The University Of California Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation
JPH0969610A (ja) * 1995-08-31 1997-03-11 Hitachi Ltd 集積半導体装置およびその製造方法
US5753955A (en) * 1996-12-19 1998-05-19 Honeywell Inc. MOS device having a gate to body connection with a body injection current limiting feature for use on silicon on insulator substrates
TW362258B (en) * 1998-03-20 1999-06-21 United Microelectronics Corp Silicon trench contact structure on the insulation layer
US6080612A (en) * 1998-05-20 2000-06-27 Sharp Laboratories Of America, Inc. Method of forming an ultra-thin SOI electrostatic discharge protection device
US6159807A (en) * 1998-09-21 2000-12-12 International Business Machines Corporation Self-aligned dynamic threshold CMOS device

Also Published As

Publication number Publication date
US20010029067A1 (en) 2001-10-11
DE10043183A1 (de) 2001-04-12
KR20010030243A (ko) 2001-04-16
JP2001077368A (ja) 2001-03-23
US6252280B1 (en) 2001-06-26
US6337230B2 (en) 2002-01-08

Similar Documents

Publication Publication Date Title
KR100340395B1 (ko) 반도체 장치 및 그 제조 방법
US7115950B2 (en) Semiconductor device and method of manufacturing the same
US6762477B2 (en) Semiconductor device
US6198134B1 (en) Semiconductor device having a common substrate bias
KR100523310B1 (ko) 반도체 장치
JP3583982B2 (ja) デュアル・ゲート電界効果トランジスタの製造方法
US20060094173A1 (en) Method for forming semiconductor device
JP2009503847A (ja) 自己整合トレンチ分離を用いた電界低減ｄｍｏｓ
KR100302189B1 (ko) 에스.오.아이(ｓｏｉ)구조를 갖는 반도체 소자 및 그 제조방법
CN100373594C (zh) 制造soi有源结构的方法和包括该结构的电路
US6232155B1 (en) Methods of fabricating semiconductor-on-insulator devices including alternating thin and thick film semiconductor regions on an insulating layer
KR970000552B1 (ko) 기판의 표면 접촉부를 갖고 있는 딥 트렌치 분리 구조물 및 이의 제조 방법
KR100422412B1 (ko) 수직 실리콘-온-인슐레이터 구조의 원통형 트랜지스터 및그 제조 방법
JPH0945904A (ja) 半導体装置およびその製造方法
KR100361764B1 (ko) 반도체소자의 소자분리막 형성방법
JP3340361B2 (ja) 半導体装置及びその製造方法
KR100607177B1 (ko) 비대칭 채널영역을 갖는 트랜지스터를 구비하는 반도체 소자 및 그 제조방법.
US6433372B1 (en) Dense multi-gated device design
KR19990002942A (ko) 에스오 아이(soi) 소자의 제조방법
KR100263475B1 (ko) 반도체 소자의 구조 및 제조 방법
JPH05299498A (ja) 半導体装置
JP2002343964A (ja) 半導体装置及びその製造方法
KR100835471B1 (ko) 반도체소자의 제조방법
JPH1093101A (ja) 半導体装置及びその製造方法
JPH0481339B2 (enExample)

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

FPAY Annual fee payment

Payment date: 20090525

Year of fee payment: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

R17-X000 Change to representative recorded

St.27 status event code: A-5-5-R10-R17-oth-X000

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20100531

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20100531

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000