KR100284467B1 - Dram센싱을위한셀플레이트기준화 - Google Patents
Dram센싱을위한셀플레이트기준화 Download PDFInfo
- Publication number
- KR100284467B1 KR100284467B1 KR1019970709066A KR19970709066A KR100284467B1 KR 100284467 B1 KR100284467 B1 KR 100284467B1 KR 1019970709066 A KR1019970709066 A KR 1019970709066A KR 19970709066 A KR19970709066 A KR 19970709066A KR 100284467 B1 KR100284467 B1 KR 100284467B1
- Authority
- KR
- South Korea
- Prior art keywords
- digit line
- node
- sense amplifier
- transistor
- sensing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Transceivers (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Semiconductor Memories (AREA)
- Investigating Or Analysing Biological Materials (AREA)
- Debugging And Monitoring (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US8/471,861 | 1995-06-06 | ||
| US08/471,861 US5719813A (en) | 1995-06-06 | 1995-06-06 | Cell plate referencing for DRAM sensing |
| PCT/US1996/009070 WO1996039698A1 (en) | 1995-06-06 | 1996-06-04 | Cell plate referencing for dram sensing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990022585A KR19990022585A (ko) | 1999-03-25 |
| KR100284467B1 true KR100284467B1 (ko) | 2001-03-02 |
Family
ID=23873269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970709066A Expired - Fee Related KR100284467B1 (ko) | 1995-06-06 | 1996-06-04 | Dram센싱을위한셀플레이트기준화 |
Country Status (9)
| Country | Link |
|---|---|
| US (2) | US5719813A (enExample) |
| EP (1) | EP0886865B1 (enExample) |
| JP (1) | JP3357898B2 (enExample) |
| KR (1) | KR100284467B1 (enExample) |
| AT (1) | ATE206556T1 (enExample) |
| AU (1) | AU6048996A (enExample) |
| DE (1) | DE69615712T2 (enExample) |
| TW (1) | TW307011B (enExample) |
| WO (1) | WO1996039698A1 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5719813A (en) * | 1995-06-06 | 1998-02-17 | Micron Technology, Inc. | Cell plate referencing for DRAM sensing |
| US5901078A (en) * | 1997-06-19 | 1999-05-04 | Micron Technology, Inc. | Variable voltage isolation gate and method |
| US6292387B1 (en) | 2000-01-20 | 2001-09-18 | Micron Technology, Inc. | Selective device coupling |
| US6301175B1 (en) | 2000-07-26 | 2001-10-09 | Micron Technology, Inc. | Memory device with single-ended sensing and low voltage pre-charge |
| US6292417B1 (en) | 2000-07-26 | 2001-09-18 | Micron Technology, Inc. | Memory device with reduced bit line pre-charge voltage |
| DE10302650B4 (de) * | 2003-01-23 | 2007-08-30 | Infineon Technologies Ag | RAM-Speicher und Steuerungsverfahren dafür |
| US7372092B2 (en) * | 2005-05-05 | 2008-05-13 | Micron Technology, Inc. | Memory cell, device, and system |
| US12347476B1 (en) * | 2022-12-27 | 2025-07-01 | Kepler Computing Inc. | Apparatus and method to improve sensing noise margin in a non-linear polar material based bit-cell |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4598387A (en) | 1983-09-29 | 1986-07-01 | Advanced Micro Devices, Inc. | Capacitive memory signal doubler cell |
| JPS60239993A (ja) * | 1984-05-12 | 1985-11-28 | Sharp Corp | ダイナミツク型半導体記憶装置 |
| US4715015A (en) * | 1984-06-01 | 1987-12-22 | Sharp Kabushiki Kaisha | Dynamic semiconductor memory with improved sense signal |
| JPS6177193A (ja) * | 1984-09-25 | 1986-04-19 | Toshiba Corp | ダイナミツク型メモリ |
| JPS62184691A (ja) * | 1986-02-08 | 1987-08-13 | Fujitsu Ltd | 半導体記憶装置 |
| JPH0336763A (ja) * | 1989-07-03 | 1991-02-18 | Hitachi Ltd | 半導体集積回路装置 |
| US5241503A (en) * | 1991-02-25 | 1993-08-31 | Motorola, Inc. | Dynamic random access memory with improved page-mode performance and method therefor having isolator between memory cells and sense amplifiers |
| JPH05159575A (ja) * | 1991-12-04 | 1993-06-25 | Oki Electric Ind Co Ltd | ダイナミックランダムアクセスメモリ |
| JPH05182458A (ja) * | 1991-12-26 | 1993-07-23 | Toshiba Corp | 半導体記憶装置 |
| JPH05242672A (ja) * | 1992-02-04 | 1993-09-21 | Nec Corp | 半導体ダイナミックメモリ |
| KR950009234B1 (ko) * | 1992-02-19 | 1995-08-18 | 삼성전자주식회사 | 반도체 메모리장치의 비트라인 분리클럭 발생장치 |
| JP3020345B2 (ja) * | 1992-05-19 | 2000-03-15 | 株式会社 沖マイクロデザイン | 半導体記憶回路 |
| JPH06215564A (ja) * | 1993-01-13 | 1994-08-05 | Nec Corp | 半導体記憶装置 |
| JPH0785675A (ja) * | 1993-09-17 | 1995-03-31 | Mitsubishi Electric Corp | 半導体記憶装置 |
| US5719813A (en) * | 1995-06-06 | 1998-02-17 | Micron Technology, Inc. | Cell plate referencing for DRAM sensing |
| US5648749A (en) * | 1995-09-19 | 1997-07-15 | Lin; Kuang Ts'an | Cartridge fuse mounting structure |
-
1995
- 1995-06-06 US US08/471,861 patent/US5719813A/en not_active Expired - Lifetime
-
1996
- 1996-06-04 WO PCT/US1996/009070 patent/WO1996039698A1/en not_active Ceased
- 1996-06-04 DE DE69615712T patent/DE69615712T2/de not_active Expired - Lifetime
- 1996-06-04 KR KR1019970709066A patent/KR100284467B1/ko not_active Expired - Fee Related
- 1996-06-04 EP EP96918166A patent/EP0886865B1/en not_active Expired - Lifetime
- 1996-06-04 AT AT96918166T patent/ATE206556T1/de not_active IP Right Cessation
- 1996-06-04 JP JP50147997A patent/JP3357898B2/ja not_active Expired - Fee Related
- 1996-06-04 AU AU60489/96A patent/AU6048996A/en not_active Abandoned
- 1996-06-26 TW TW085107682A patent/TW307011B/zh not_active IP Right Cessation
-
1998
- 1998-02-17 US US09/024,440 patent/US5894444A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| AU6048996A (en) | 1996-12-24 |
| TW307011B (enExample) | 1997-06-01 |
| DE69615712T2 (de) | 2002-04-18 |
| US5719813A (en) | 1998-02-17 |
| US5894444A (en) | 1999-04-13 |
| KR19990022585A (ko) | 1999-03-25 |
| EP0886865A1 (en) | 1998-12-30 |
| EP0886865B1 (en) | 2001-10-04 |
| WO1996039698A1 (en) | 1996-12-12 |
| JPH10507863A (ja) | 1998-07-28 |
| ATE206556T1 (de) | 2001-10-15 |
| JP3357898B2 (ja) | 2002-12-16 |
| DE69615712D1 (de) | 2001-11-08 |
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| Publication | Publication Date | Title |
|---|---|---|
| JP3470722B2 (ja) | アレイ・エッジ部での基準検知を具備するdram | |
| KR100276540B1 (ko) | 저전압 다이나믹 메모리 | |
| KR100284468B1 (ko) | Dram의글로벌비트라인을이용한싱글-엔드센싱 | |
| JPH057796B2 (enExample) | ||
| US6266287B1 (en) | Variable equilibrate voltage circuit for paired digit lines | |
| US4622655A (en) | Semiconductor memory | |
| US6301175B1 (en) | Memory device with single-ended sensing and low voltage pre-charge | |
| US6292417B1 (en) | Memory device with reduced bit line pre-charge voltage | |
| KR100284467B1 (ko) | Dram센싱을위한셀플레이트기준화 | |
| US5831895A (en) | Dynamic cell plate sensing and equilibration in a memory device | |
| US5923603A (en) | Equilibrate circuit for dynamic plate sensing memories | |
| US5745423A (en) | Low power precharge circuit for a dynamic random access memory | |
| JP2980368B2 (ja) | ダイナミック型半導体記憶装置 | |
| US5430686A (en) | Semiconductor memory device and operating method thereof | |
| JPH06101229B2 (ja) | ダイナミツク・ランダム・アクセス・メモリ | |
| US4734890A (en) | Dynamic RAM having full-sized dummy cell | |
| KR20050084162A (ko) | 상이한 메모리 어레이들의 열들에 의해 공유되는 전류 제한블리더 장치를 위한 장치 및 방법 | |
| JPH08249885A (ja) | ダイナミック型半導体記憶装置 |
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