ATE206556T1 - Zellengegenplatteneinstellung für dram- leseoperation - Google Patents

Zellengegenplatteneinstellung für dram- leseoperation

Info

Publication number
ATE206556T1
ATE206556T1 AT96918166T AT96918166T ATE206556T1 AT E206556 T1 ATE206556 T1 AT E206556T1 AT 96918166 T AT96918166 T AT 96918166T AT 96918166 T AT96918166 T AT 96918166T AT E206556 T1 ATE206556 T1 AT E206556T1
Authority
AT
Austria
Prior art keywords
cell
counterplate
adjustment
reading operation
circuitry
Prior art date
Application number
AT96918166T
Other languages
German (de)
English (en)
Inventor
Mirmajid Seyyedy
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE206556T1 publication Critical patent/ATE206556T1/de

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4094Bit-line management or control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Transceivers (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Semiconductor Memories (AREA)
  • Investigating Or Analysing Biological Materials (AREA)
  • Debugging And Monitoring (AREA)
AT96918166T 1995-06-06 1996-06-04 Zellengegenplatteneinstellung für dram- leseoperation ATE206556T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/471,861 US5719813A (en) 1995-06-06 1995-06-06 Cell plate referencing for DRAM sensing
PCT/US1996/009070 WO1996039698A1 (en) 1995-06-06 1996-06-04 Cell plate referencing for dram sensing

Publications (1)

Publication Number Publication Date
ATE206556T1 true ATE206556T1 (de) 2001-10-15

Family

ID=23873269

Family Applications (1)

Application Number Title Priority Date Filing Date
AT96918166T ATE206556T1 (de) 1995-06-06 1996-06-04 Zellengegenplatteneinstellung für dram- leseoperation

Country Status (9)

Country Link
US (2) US5719813A (enExample)
EP (1) EP0886865B1 (enExample)
JP (1) JP3357898B2 (enExample)
KR (1) KR100284467B1 (enExample)
AT (1) ATE206556T1 (enExample)
AU (1) AU6048996A (enExample)
DE (1) DE69615712T2 (enExample)
TW (1) TW307011B (enExample)
WO (1) WO1996039698A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5719813A (en) * 1995-06-06 1998-02-17 Micron Technology, Inc. Cell plate referencing for DRAM sensing
US5901078A (en) * 1997-06-19 1999-05-04 Micron Technology, Inc. Variable voltage isolation gate and method
US6292387B1 (en) 2000-01-20 2001-09-18 Micron Technology, Inc. Selective device coupling
US6301175B1 (en) 2000-07-26 2001-10-09 Micron Technology, Inc. Memory device with single-ended sensing and low voltage pre-charge
US6292417B1 (en) 2000-07-26 2001-09-18 Micron Technology, Inc. Memory device with reduced bit line pre-charge voltage
DE10302650B4 (de) * 2003-01-23 2007-08-30 Infineon Technologies Ag RAM-Speicher und Steuerungsverfahren dafür
US7372092B2 (en) * 2005-05-05 2008-05-13 Micron Technology, Inc. Memory cell, device, and system
US12347476B1 (en) * 2022-12-27 2025-07-01 Kepler Computing Inc. Apparatus and method to improve sensing noise margin in a non-linear polar material based bit-cell

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4598387A (en) 1983-09-29 1986-07-01 Advanced Micro Devices, Inc. Capacitive memory signal doubler cell
JPS60239993A (ja) * 1984-05-12 1985-11-28 Sharp Corp ダイナミツク型半導体記憶装置
US4715015A (en) * 1984-06-01 1987-12-22 Sharp Kabushiki Kaisha Dynamic semiconductor memory with improved sense signal
JPS6177193A (ja) * 1984-09-25 1986-04-19 Toshiba Corp ダイナミツク型メモリ
JPS62184691A (ja) * 1986-02-08 1987-08-13 Fujitsu Ltd 半導体記憶装置
JPH0336763A (ja) * 1989-07-03 1991-02-18 Hitachi Ltd 半導体集積回路装置
US5241503A (en) * 1991-02-25 1993-08-31 Motorola, Inc. Dynamic random access memory with improved page-mode performance and method therefor having isolator between memory cells and sense amplifiers
JPH05159575A (ja) * 1991-12-04 1993-06-25 Oki Electric Ind Co Ltd ダイナミックランダムアクセスメモリ
JPH05182458A (ja) * 1991-12-26 1993-07-23 Toshiba Corp 半導体記憶装置
JPH05242672A (ja) * 1992-02-04 1993-09-21 Nec Corp 半導体ダイナミックメモリ
KR950009234B1 (ko) * 1992-02-19 1995-08-18 삼성전자주식회사 반도체 메모리장치의 비트라인 분리클럭 발생장치
JP3020345B2 (ja) * 1992-05-19 2000-03-15 株式会社 沖マイクロデザイン 半導体記憶回路
JPH06215564A (ja) * 1993-01-13 1994-08-05 Nec Corp 半導体記憶装置
JPH0785675A (ja) * 1993-09-17 1995-03-31 Mitsubishi Electric Corp 半導体記憶装置
US5719813A (en) * 1995-06-06 1998-02-17 Micron Technology, Inc. Cell plate referencing for DRAM sensing
US5648749A (en) * 1995-09-19 1997-07-15 Lin; Kuang Ts'an Cartridge fuse mounting structure

Also Published As

Publication number Publication date
AU6048996A (en) 1996-12-24
KR100284467B1 (ko) 2001-03-02
TW307011B (enExample) 1997-06-01
DE69615712T2 (de) 2002-04-18
US5719813A (en) 1998-02-17
US5894444A (en) 1999-04-13
KR19990022585A (ko) 1999-03-25
EP0886865A1 (en) 1998-12-30
EP0886865B1 (en) 2001-10-04
WO1996039698A1 (en) 1996-12-12
JPH10507863A (ja) 1998-07-28
JP3357898B2 (ja) 2002-12-16
DE69615712D1 (de) 2001-11-08

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Legal Events

Date Code Title Description
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