KR100223729B1 - 살리사이드 반도체 장치 제조 방법 - Google Patents

살리사이드 반도체 장치 제조 방법 Download PDF

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Publication number
KR100223729B1
KR100223729B1 KR1019960003510A KR19960003510A KR100223729B1 KR 100223729 B1 KR100223729 B1 KR 100223729B1 KR 1019960003510 A KR1019960003510 A KR 1019960003510A KR 19960003510 A KR19960003510 A KR 19960003510A KR 100223729 B1 KR100223729 B1 KR 100223729B1
Authority
KR
South Korea
Prior art keywords
layer
polycrystalline silicon
gate electrode
impurity
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019960003510A
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English (en)
Korean (ko)
Inventor
도오루 모가미
Original Assignee
가네꼬 히사시
닛본 덴기 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP7049037A external-priority patent/JP2842284B2/ja
Priority claimed from JP7129771A external-priority patent/JP2827962B2/ja
Application filed by 가네꼬 히사시, 닛본 덴기 가부시끼가이샤 filed Critical 가네꼬 히사시
Application granted granted Critical
Publication of KR100223729B1 publication Critical patent/KR100223729B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/0131—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0174—Manufacturing their gate conductors the gate conductors being silicided
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1019960003510A 1995-02-14 1996-02-14 살리사이드 반도체 장치 제조 방법 Expired - Fee Related KR100223729B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP95-049037 1995-02-14
JP7049037A JP2842284B2 (ja) 1995-02-14 1995-02-14 半導体装置の製造方法
JP7129771A JP2827962B2 (ja) 1995-04-28 1995-04-28 半導体装置の製造方法
JP95-129771 1995-04-28

Publications (1)

Publication Number Publication Date
KR100223729B1 true KR100223729B1 (ko) 1999-10-15

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960003510A Expired - Fee Related KR100223729B1 (ko) 1995-02-14 1996-02-14 살리사이드 반도체 장치 제조 방법

Country Status (4)

Country Link
US (1) US5656519A (enExample)
EP (1) EP0727815B1 (enExample)
KR (1) KR100223729B1 (enExample)
DE (1) DE69600261T2 (enExample)

Families Citing this family (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2792467B2 (ja) * 1995-06-13 1998-09-03 日本電気株式会社 半導体装置の製造方法
TW304278B (en) * 1996-09-17 1997-05-01 Nat Science Council The source-drain distributed implantation method
US5923999A (en) * 1996-10-29 1999-07-13 International Business Machines Corporation Method of controlling dopant diffusion and metal contamination in thin polycide gate conductor of mosfet device
JPH10223889A (ja) * 1997-02-04 1998-08-21 Mitsubishi Electric Corp Ｍｉｓトランジスタおよびその製造方法
US5930634A (en) * 1997-04-21 1999-07-27 Advanced Micro Devices, Inc. Method of making an IGFET with a multilevel gate
US6074921A (en) * 1997-06-30 2000-06-13 Vlsi Technology, Inc. Self-aligned processing of semiconductor device features
US6261887B1 (en) * 1997-08-28 2001-07-17 Texas Instruments Incorporated Transistors with independently formed gate structures and method
KR100268871B1 (ko) * 1997-09-26 2000-10-16 김영환 반도체소자의제조방법
JPH11135745A (ja) * 1997-10-29 1999-05-21 Toshiba Corp 半導体装置及びその製造方法
US6048784A (en) * 1997-12-17 2000-04-11 Texas Instruments Incorporated Transistor having an improved salicided gate and method of construction
US6083836A (en) * 1997-12-23 2000-07-04 Texas Instruments Incorporated Transistors with substitutionally formed gate structures and method
US6274421B1 (en) 1998-01-09 2001-08-14 Sharp Laboratories Of America, Inc. Method of making metal gate sub-micron MOS transistor
KR19990065891A (ko) * 1998-01-19 1999-08-05 구본준 통합 반도체 소자의 제조방법
US6118163A (en) * 1998-02-04 2000-09-12 Advanced Micro Devices, Inc. Transistor with integrated poly/metal gate electrode
US6147405A (en) 1998-02-19 2000-11-14 Micron Technology, Inc. Asymmetric, double-sided self-aligned silicide and method of forming the same
US6133106A (en) * 1998-02-23 2000-10-17 Sharp Laboratories Of America, Inc. Fabrication of a planar MOSFET with raised source/drain by chemical mechanical polishing and nitride replacement
US6136636A (en) * 1998-03-25 2000-10-24 Texas Instruments - Acer Incorporated Method of manufacturing deep sub-micron CMOS transistors
US6649308B1 (en) * 1998-03-30 2003-11-18 Texas Instruments-Acer Incorporated Ultra-short channel NMOSFETS with self-aligned silicide contact
US5930617A (en) * 1998-03-25 1999-07-27 Texas Instruments-Acer Incorporated Method of forming deep sub-micron CMOS transistors with self-aligned silicided contact and extended S/D junction
US5956584A (en) * 1998-03-30 1999-09-21 Texas Instruments - Acer Incorporated Method of making self-aligned silicide CMOS transistors
US6090653A (en) * 1998-03-30 2000-07-18 Texas Instruments Method of manufacturing CMOS transistors
TW372349B (en) * 1998-06-08 1999-10-21 United Microelectronics Corp Bridge prevention method for self-aligned metal silicide
US6265256B1 (en) * 1998-09-17 2001-07-24 Advanced Micro Devices, Inc. MOS transistor with minimal overlap between gate and source/drain extensions
US6265252B1 (en) 1999-05-03 2001-07-24 Vlsi Technology, Inc. Reducing the formation of electrical leakage pathways during manufacture of an electronic device
US6194299B1 (en) * 1999-06-03 2001-02-27 Advanced Micro Devices, Inc. Method for fabrication of a low resistivity MOSFET gate with thick metal on polysilicon
US6251732B1 (en) * 1999-08-10 2001-06-26 Macronix International Co., Ltd. Method and apparatus for forming self-aligned code structures for semi conductor devices
US6297109B1 (en) * 1999-08-19 2001-10-02 Chartered Semiconductor Manufacturing Ltd. Method to form shallow junction transistors while eliminating shorts due to junction spiking
US6200886B1 (en) * 1999-10-28 2001-03-13 United Silicon Incorporated Fabricating process for polysilicon gate
US6271106B1 (en) * 1999-10-29 2001-08-07 Motorola, Inc. Method of manufacturing a semiconductor component
JP2001237422A (ja) * 1999-12-14 2001-08-31 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US6294448B1 (en) 2000-01-18 2001-09-25 Taiwan Semiconductor Manufacturing Company Method to improve TiSix salicide formation
JP2001210726A (ja) * 2000-01-24 2001-08-03 Hitachi Ltd 半導体装置及びその製造方法
US6294433B1 (en) * 2000-02-09 2001-09-25 Advanced Micro Devices, Inc. Gate re-masking for deeper source/drain co-implantation processes
JP3490046B2 (ja) * 2000-05-02 2004-01-26 シャープ株式会社 半導体装置及びその製造方法
US6458678B1 (en) * 2000-07-25 2002-10-01 Advanced Micro Devices, Inc. Transistor formed using a dual metal process for gate and source/drain region
US6664740B2 (en) 2001-02-01 2003-12-16 The Regents Of The University Of California Formation of a field reversed configuration for magnetic and electrostatic confinement of plasma
US6524939B2 (en) 2001-02-23 2003-02-25 Vanguard International Semiconductor Corporation Dual salicidation process
US6528402B2 (en) * 2001-02-23 2003-03-04 Vanguard International Semiconductor Corporation Dual salicidation process
US6611106B2 (en) * 2001-03-19 2003-08-26 The Regents Of The University Of California Controlled fusion in a field reversed configuration and direct energy conversion
US6518154B1 (en) * 2001-03-21 2003-02-11 Advanced Micro Devices, Inc. Method of forming semiconductor devices with differently composed metal-based gate electrodes
US6624043B2 (en) * 2001-09-24 2003-09-23 Sharp Laboratories Of America, Inc. Metal gate CMOS and method of manufacturing the same
DE10208904B4 (de) 2002-02-28 2007-03-01 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung unterschiedlicher Silicidbereiche auf verschiedenen Silicium enthaltenden Gebieten in einem Halbleiterelement
DE10208728B4 (de) 2002-02-28 2009-05-07 Advanced Micro Devices, Inc., Sunnyvale Ein Verfahren zur Herstellung eines Halbleiterelements mit unterschiedlichen Metallsilizidbereichen
AU2002359813A1 (en) * 2002-03-01 2003-09-16 Advanced Micro Devices, Inc. A semiconductor device having different metal-semiconductor portions formed in a semiconductor region and a method for fabricating the semiconductor device
JP2003297956A (ja) * 2002-04-04 2003-10-17 Toshiba Corp 半導体記憶装置及びその製造方法
DE10234931A1 (de) 2002-07-31 2004-02-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Metallsilizidgates in einer standardmässigen MOS-Prozesssequenz
US6815235B1 (en) 2002-11-25 2004-11-09 Advanced Micro Devices, Inc. Methods of controlling formation of metal silicide regions, and system for performing same
US7153772B2 (en) 2003-06-12 2006-12-26 Asm International N.V. Methods of forming silicide films in semiconductor devices
US9123512B2 (en) 2005-03-07 2015-09-01 The Regents Of The Unviersity Of California RF current drive for plasma electric generation system
US8031824B2 (en) 2005-03-07 2011-10-04 Regents Of The University Of California Inductive plasma source for plasma electric generation system
US9607719B2 (en) * 2005-03-07 2017-03-28 The Regents Of The University Of California Vacuum chamber for plasma electric generation system
EP1894243A2 (en) * 2005-06-16 2008-03-05 Nxp B.V. Semiconductor device having a polysilicon electrode
JP2007073760A (ja) * 2005-09-07 2007-03-22 Matsushita Electric Ind Co Ltd Ｍｏｓトランジスタセル及び半導体装置
US8278176B2 (en) 2006-06-07 2012-10-02 Asm America, Inc. Selective epitaxial formation of semiconductor films
US8367548B2 (en) 2007-03-16 2013-02-05 Asm America, Inc. Stable silicide films and methods for making the same
JP2009076731A (ja) * 2007-09-21 2009-04-09 Renesas Technology Corp 半導体装置およびその製造方法
CN101752314B (zh) * 2008-12-04 2012-10-03 上海华虹Nec电子有限公司 具有自对准接触孔的表面沟道pmos器件及制作方法
CN101752313B (zh) * 2008-12-04 2012-10-03 上海华虹Nec电子有限公司 一种具有自对准接触孔的表面沟道pmos器件及制作方法
US9379011B2 (en) 2008-12-19 2016-06-28 Asm International N.V. Methods for depositing nickel films and for making nickel silicide and nickel germanide
US7927942B2 (en) 2008-12-19 2011-04-19 Asm International N.V. Selective silicide process
US8367528B2 (en) 2009-11-17 2013-02-05 Asm America, Inc. Cyclical epitaxial deposition and etch
US8871617B2 (en) 2011-04-22 2014-10-28 Asm Ip Holding B.V. Deposition and reduction of mixed metal oxide thin films
US8809170B2 (en) 2011-05-19 2014-08-19 Asm America Inc. High throughput cyclical epitaxial deposition and etch process
SG10201704299XA (en) 2011-11-14 2017-06-29 Univ California Systems and methods for forming and maintaining a high performance frc
AU2014326799A1 (en) 2013-09-24 2016-04-07 Tae Technologies, Inc. Systems and methods for forming and maintaining a high performance FRC
SG11201702830UA (en) 2014-10-13 2017-05-30 Tri Alpha Energy Inc Systems and methods for merging and compressing compact tori
EP3589083B1 (en) 2014-10-30 2022-08-24 TAE Technologies, Inc. Systems for forming and maintaining a high performance frc
ES2837256T3 (es) 2015-05-12 2021-06-29 Tae Tech Inc Sistemas y procedimientos para reducir corrientes de Foucault no deseadas
US9607842B1 (en) 2015-10-02 2017-03-28 Asm Ip Holding B.V. Methods of forming metal silicides
WO2017083796A1 (en) 2015-11-13 2017-05-18 Tri Alpha Energy, Inc. Systems and methods for frc plasma position stability
SG11201903545VA (en) 2016-10-28 2019-05-30 Tae Technologies Inc Systems and methods for improved sustainment of a high performance frc elevated energies utilizing neutral beam injectors with tunable beam energies
MX2019005262A (es) 2016-11-04 2019-06-24 Tae Tech Inc Sistemas y metodos para un mantenimiento mejorado de una configuracion de campo invertido (frc) de alto rendimiento con bombeo de vacio de tipo captura de escala multiple.
IL266612B2 (en) 2016-11-15 2024-04-01 Tae Tech Inc Systems and methods for improved sustainment of a high performance frc and high harmonic fast wave electron heating in a high performance frc
WO2021146329A1 (en) 2020-01-13 2021-07-22 Tae Technologies, Inc. System and methods for forming and maintaining high energy and temperature frc plasma via spheromak merging and neutral beam injection

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1987006764A1 (en) * 1986-04-23 1987-11-05 American Telephone & Telegraph Company Process for manufacturing semiconductor devices
CA1306072C (en) * 1987-03-30 1992-08-04 John E. Cronin Refractory metal - titanium nitride conductive structures and processes for forming the same
JPH0227737A (ja) * 1988-07-15 1990-01-30 Nec Corp 半導体装置の製造方法
US4998150A (en) * 1988-12-22 1991-03-05 Texas Instruments Incorporated Raised source/drain transistor
JP2793248B2 (ja) * 1989-04-28 1998-09-03 日本電気株式会社 半導体・素子構造の製造方法
US4948745A (en) * 1989-05-22 1990-08-14 Motorola, Inc. Process for elevated source/drain field effect structure
JPH03288443A (ja) * 1990-04-04 1991-12-18 Oki Electric Ind Co Ltd 半導体装置の製造方法
US5164333A (en) * 1990-06-19 1992-11-17 Siemens Aktiengesellschaft Method for manufacturing a multi-layer gate electrode for a mos transistor
US5168072A (en) * 1990-10-12 1992-12-01 Texas Instruments Incorporated Method of fabricating an high-performance insulated-gate field-effect transistor
US5322809A (en) * 1993-05-11 1994-06-21 Texas Instruments Incorporated Self-aligned silicide process

Also Published As

Publication number Publication date
EP0727815B1 (en) 1998-04-29
EP0727815A2 (en) 1996-08-21
US5656519A (en) 1997-08-12
DE69600261D1 (de) 1998-06-04
EP0727815A3 (enExample) 1996-09-25
DE69600261T2 (de) 1998-10-15

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