KR0137756B1 - 동기형 다이나믹 ram - Google Patents

동기형 다이나믹 ram

Info

Publication number
KR0137756B1
KR0137756B1 KR1019910017761A KR910017761A KR0137756B1 KR 0137756 B1 KR0137756 B1 KR 0137756B1 KR 1019910017761 A KR1019910017761 A KR 1019910017761A KR 910017761 A KR910017761 A KR 910017761A KR 0137756 B1 KR0137756 B1 KR 0137756B1
Authority
KR
South Korea
Prior art keywords
circuit
output
clock
data
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019910017761A
Other languages
English (en)
Korean (ko)
Other versions
KR920010631A (ko
Inventor
아쓰시 다까스기
Original Assignee
고스기 노부미쓰
오끼덴끼고오교 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 고스기 노부미쓰, 오끼덴끼고오교 가부시끼가이샤 filed Critical 고스기 노부미쓰
Publication of KR920010631A publication Critical patent/KR920010631A/ko
Application granted granted Critical
Publication of KR0137756B1 publication Critical patent/KR0137756B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
KR1019910017761A 1990-11-20 1991-10-10 동기형 다이나믹 ram Expired - Fee Related KR0137756B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP90-316522 1990-11-20
JP31652290 1990-11-20

Publications (2)

Publication Number Publication Date
KR920010631A KR920010631A (ko) 1992-06-26
KR0137756B1 true KR0137756B1 (ko) 1998-06-01

Family

ID=18078048

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910017761A Expired - Fee Related KR0137756B1 (ko) 1990-11-20 1991-10-10 동기형 다이나믹 ram

Country Status (6)

Country Link
US (1) US5311483A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0511408B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR0137756B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE69129016T2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
TW (1) TW198135B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
WO (1) WO1992009083A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

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GB9007791D0 (en) * 1990-04-06 1990-06-06 Foss Richard C High voltage boosted wordline supply charge pump and regulator for dram
GB9007790D0 (en) * 1990-04-06 1990-06-06 Lines Valerie L Dynamic memory wordline driver scheme
US6310821B1 (en) * 1998-07-10 2001-10-30 Kabushiki Kaisha Toshiba Clock-synchronous semiconductor memory device and access method thereof
DE69325119T2 (de) * 1992-03-19 1999-11-04 Kabushiki Kaisha Toshiba, Kawasaki Taktsynchronisierter Halbleiterspeicheranordnung und Zugriffsverfahren
KR950010564B1 (en) * 1992-10-02 1995-09-19 Samsung Electronics Co Ltd Data output buffer of synchronous semiconductor memory device
US6279116B1 (en) 1992-10-02 2001-08-21 Samsung Electronics Co., Ltd. Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation
JP2605576B2 (ja) * 1993-04-02 1997-04-30 日本電気株式会社 同期型半導体メモリ
US5594699A (en) * 1993-09-20 1997-01-14 Fujitsu Limited DRAM with reduced electric power consumption
JP3080520B2 (ja) * 1993-09-21 2000-08-28 富士通株式会社 シンクロナスｄｒａｍ
DE69432455T2 (de) * 1993-12-16 2003-11-20 Fujitsu Ltd., Kawasaki Ausgangpuffer mit variabler Latenz und Synchronisiereinrichtung für synchronen Speicher
JP3304577B2 (ja) * 1993-12-24 2002-07-22 三菱電機株式会社 半導体記憶装置とその動作方法
IL110181A (en) * 1994-06-30 1998-02-08 Softchip Israel Ltd Install microprocessor and peripherals
US5796673A (en) 1994-10-06 1998-08-18 Mosaid Technologies Incorporated Delay locked loop implementation in a synchronous dynamic random access memory
JP3161254B2 (ja) 1994-11-25 2001-04-25 株式会社日立製作所 同期式メモリ装置
US5513148A (en) * 1994-12-01 1996-04-30 Micron Technology Inc. Synchronous NAND DRAM architecture
US5577236A (en) * 1994-12-30 1996-11-19 International Business Machines Corporation Memory controller for reading data from synchronous RAM
US5559753A (en) * 1995-01-25 1996-09-24 Dell Usa, L.P. Apparatus and method for preventing bus contention during power-up in a computer system with two or more DRAM banks
US5630096A (en) * 1995-05-10 1997-05-13 Microunity Systems Engineering, Inc. Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order
JPH0969292A (ja) * 1995-08-30 1997-03-11 Nec Corp 半導体記憶装置
US5692165A (en) * 1995-09-12 1997-11-25 Micron Electronics Inc. Memory controller with low skew control signal
US6470405B2 (en) 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US6810449B1 (en) 1995-10-19 2004-10-26 Rambus, Inc. Protocol for communication with dynamic memory
US6035369A (en) 1995-10-19 2000-03-07 Rambus Inc. Method and apparatus for providing a memory with write enable information
JP3566429B2 (ja) * 1995-12-19 2004-09-15 株式会社ルネサステクノロジ 同期型半導体記憶装置
KR100412061B1 (ko) * 1996-03-30 2004-04-06 삼성전자주식회사 싱크 디램 데이타 패스에서의 시스템 클럭 동기 방법
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
US6115318A (en) * 1996-12-03 2000-09-05 Micron Technology, Inc. Clock vernier adjustment
US5940608A (en) 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
US6912680B1 (en) 1997-02-11 2005-06-28 Micron Technology, Inc. Memory system with dynamic timing correction
US5946244A (en) 1997-03-05 1999-08-31 Micron Technology, Inc. Delay-locked loop with binary-coupled capacitor
US6266379B1 (en) 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
US6173432B1 (en) * 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US5953284A (en) * 1997-07-09 1999-09-14 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
US6011732A (en) * 1997-08-20 2000-01-04 Micron Technology, Inc. Synchronous clock generator including a compound delay-locked loop
US5978284A (en) 1997-08-22 1999-11-02 Micron Technology, Inc. Synchronous memory with programmable read latency
US5926047A (en) 1997-08-29 1999-07-20 Micron Technology, Inc. Synchronous clock generator including a delay-locked loop signal loss detector
US5940609A (en) * 1997-08-29 1999-08-17 Micorn Technology, Inc. Synchronous clock generator including a false lock detector
US6101197A (en) * 1997-09-18 2000-08-08 Micron Technology, Inc. Method and apparatus for adjusting the timing of signals over fine and coarse ranges
WO1999019805A1 (en) 1997-10-10 1999-04-22 Rambus Incorporated Method and apparatus for two step memory write operations
US6263448B1 (en) 1997-10-10 2001-07-17 Rambus Inc. Power control system for synchronous memory device
US6401167B1 (en) * 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
US6011749A (en) * 1998-03-27 2000-01-04 Motorola, Inc. Integrated circuit having output timing control circuit and method thereof
US6016282A (en) * 1998-05-28 2000-01-18 Micron Technology, Inc. Clock vernier adjustment
US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6349399B1 (en) 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
US6029250A (en) * 1998-09-09 2000-02-22 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US6470060B1 (en) * 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
JP4266436B2 (ja) * 1999-04-28 2009-05-20 富士通マイクロエレクトロニクス株式会社 半導体記憶装置
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US8391039B2 (en) * 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US6801989B2 (en) * 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US7076678B2 (en) 2002-02-11 2006-07-11 Micron Technology, Inc. Method and apparatus for data transfer
US7168027B2 (en) 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
US7234070B2 (en) 2003-10-27 2007-06-19 Micron Technology, Inc. System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
KR100612950B1 (ko) * 2004-04-22 2006-08-14 주식회사 하이닉스반도체 외부클럭을 사용한 디램의 라스타임 제어회로 및 라스타임제어방법
US7301831B2 (en) 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
KR100803359B1 (ko) * 2006-08-11 2008-02-14 주식회사 하이닉스반도체 반도체 메모리 장치의 데이터 입력 회로 및 방법
KR100772842B1 (ko) 2006-08-22 2007-11-02 삼성전자주식회사 데이터 패쓰 조절기능을 갖는 반도체 메모리 장치

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JPS61110396A (ja) * 1984-11-05 1986-05-28 Fujitsu Ltd 半導体記憶装置
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US4823302A (en) * 1987-01-30 1989-04-18 Rca Licensing Corporation Block oriented random access memory able to perform a data read, a data write and a data refresh operation in one block-access time
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JPH02105389A (ja) * 1988-10-13 1990-04-17 Matsushita Electron Corp ダイナミック型記憶装置

Also Published As

Publication number Publication date
TW198135B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-01-11
EP0511408A1 (en) 1992-11-04
KR920010631A (ko) 1992-06-26
EP0511408A4 (en) 1993-07-28
US5311483A (en) 1994-05-10
WO1992009083A1 (fr) 1992-05-29
EP0511408B1 (en) 1998-03-04
DE69129016T2 (de) 1998-10-01
DE69129016D1 (de) 1998-04-09

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