KR0126801B1 - 반도체 장치의 배선 형성방법 - Google Patents

반도체 장치의 배선 형성방법

Info

Publication number
KR0126801B1
KR0126801B1 KR1019930029052A KR930029052A KR0126801B1 KR 0126801 B1 KR0126801 B1 KR 0126801B1 KR 1019930029052 A KR1019930029052 A KR 1019930029052A KR 930029052 A KR930029052 A KR 930029052A KR 0126801 B1 KR0126801 B1 KR 0126801B1
Authority
KR
South Korea
Prior art keywords
insulating layer
etching
conductive layer
forming
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019930029052A
Other languages
English (en)
Korean (ko)
Other versions
KR950021085A (ko
Inventor
김재우
김준
김진홍
Original Assignee
김광호
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자주식회사 filed Critical 김광호
Priority to KR1019930029052A priority Critical patent/KR0126801B1/ko
Priority to TW083111682A priority patent/TW289130B/zh
Priority to JP31674294A priority patent/JP3571784B2/ja
Priority to US08/361,835 priority patent/US5591675A/en
Publication of KR950021085A publication Critical patent/KR950021085A/ko
Application granted granted Critical
Publication of KR0126801B1 publication Critical patent/KR0126801B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/161—Tapered edges

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
KR1019930029052A 1993-12-22 1993-12-22 반도체 장치의 배선 형성방법 Expired - Fee Related KR0126801B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019930029052A KR0126801B1 (ko) 1993-12-22 1993-12-22 반도체 장치의 배선 형성방법
TW083111682A TW289130B (enExample) 1993-12-22 1994-12-14
JP31674294A JP3571784B2 (ja) 1993-12-22 1994-12-20 半導体装置の配線形成方法
US08/361,835 US5591675A (en) 1993-12-22 1994-12-22 Interconnecting method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930029052A KR0126801B1 (ko) 1993-12-22 1993-12-22 반도체 장치의 배선 형성방법

Publications (2)

Publication Number Publication Date
KR950021085A KR950021085A (ko) 1995-07-26
KR0126801B1 true KR0126801B1 (ko) 1998-04-02

Family

ID=19372111

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930029052A Expired - Fee Related KR0126801B1 (ko) 1993-12-22 1993-12-22 반도체 장치의 배선 형성방법

Country Status (4)

Country Link
US (1) US5591675A (enExample)
JP (1) JP3571784B2 (enExample)
KR (1) KR0126801B1 (enExample)
TW (1) TW289130B (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09153545A (ja) * 1995-09-29 1997-06-10 Toshiba Corp 半導体装置及びその製造方法
KR100390832B1 (ko) * 1995-11-06 2003-09-22 주식회사 하이닉스반도체 반도체소자제조공정에서의폴리머제거방법
DE19609229C2 (de) * 1996-03-09 1998-10-15 Micronas Intermetall Gmbh Verfahren zum Herstellen von diskreten elektronischen Elementen
US5746884A (en) * 1996-08-13 1998-05-05 Advanced Micro Devices, Inc. Fluted via formation for superior metal step coverage
US5661084A (en) * 1996-10-04 1997-08-26 Taiwan Semiconductor Manufacturing Company, Ltd Method for contact profile improvement
KR100402940B1 (ko) * 1996-11-13 2004-04-14 주식회사 하이닉스반도체 반도체 소자의 다중 금속층 형성 방법
US6271117B1 (en) * 1997-06-23 2001-08-07 Vanguard International Semiconductor Corporation Process for a nail shaped landing pad plug
US6042887A (en) * 1998-01-12 2000-03-28 Taiwan Semiconductor Manufacturing Company Process for forming a sausg inter metal dielectric layer by pre-coating the reactor
US6274393B1 (en) 1998-04-20 2001-08-14 International Business Machines Corporation Method for measuring submicron images
US6054384A (en) * 1998-05-19 2000-04-25 Advanced Micro Devices, Inc. Use of hard masks during etching of openings in integrated circuits for high etch selectivity
US6727180B2 (en) * 1999-02-06 2004-04-27 United Microelectronics Corp. Method for forming contact window
US6235638B1 (en) * 1999-02-16 2001-05-22 Micron Technology, Inc. Simplified etching technique for producing multiple undercut profiles
JP2002110647A (ja) * 2000-09-29 2002-04-12 Hitachi Ltd 半導体集積回路装置の製造方法
US6852592B2 (en) * 2002-06-03 2005-02-08 Hynix Semiconductor, Inc. Methods for fabricating semiconductor devices
KR100940665B1 (ko) * 2007-11-29 2010-02-05 주식회사 동부하이텍 반도체 소자의 제조 방법
CN101645408B (zh) * 2008-08-04 2012-05-16 中芯国际集成电路制造(北京)有限公司 焊盘及其形成方法
JP5551887B2 (ja) * 2009-03-31 2014-07-16 ラピスセミコンダクタ株式会社 半導体素子の製造方法
US9917027B2 (en) * 2015-12-30 2018-03-13 Globalfoundries Singapore Pte. Ltd. Integrated circuits with aluminum via structures and methods for fabricating the same
JP6725317B2 (ja) * 2016-05-19 2020-07-15 株式会社ジャパンディスプレイ 表示装置
US20210020455A1 (en) * 2019-07-17 2021-01-21 Nanya Technology Corporation Conductive via structure
DE102019133935B4 (de) * 2019-09-30 2022-11-03 Taiwan Semiconductor Manufacturing Co. Ltd. Verfahren zum ausbilden von transistorabstandshal-terstrukturen

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0773104B2 (ja) * 1986-02-14 1995-08-02 富士通株式会社 レジスト剥離方法
EP0263220B1 (en) * 1986-10-08 1992-09-09 International Business Machines Corporation Method of forming a via-having a desired slope in a photoresist masked composite insulating layer
JPS63258021A (ja) * 1987-04-16 1988-10-25 Toshiba Corp 接続孔の形成方法
JP2659980B2 (ja) * 1988-01-28 1997-09-30 株式会社東芝 半導体装置の製造方法
JP2660359B2 (ja) * 1991-01-30 1997-10-08 三菱電機株式会社 半導体装置
US5420078A (en) * 1991-08-14 1995-05-30 Vlsi Technology, Inc. Method for producing via holes in integrated circuit layers

Also Published As

Publication number Publication date
TW289130B (enExample) 1996-10-21
JPH07211718A (ja) 1995-08-11
KR950021085A (ko) 1995-07-26
US5591675A (en) 1997-01-07
JP3571784B2 (ja) 2004-09-29

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