JPWO2020236611A5 - - Google Patents
Download PDFInfo
- Publication number
- JPWO2020236611A5 JPWO2020236611A5 JP2021559384A JP2021559384A JPWO2020236611A5 JP WO2020236611 A5 JPWO2020236611 A5 JP WO2020236611A5 JP 2021559384 A JP2021559384 A JP 2021559384A JP 2021559384 A JP2021559384 A JP 2021559384A JP WO2020236611 A5 JPWO2020236611 A5 JP WO2020236611A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- forming
- active
- semiconductor layer
- data storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201962849770P | 2019-05-17 | 2019-05-17 | |
| US62/849,770 | 2019-05-17 | ||
| PCT/US2020/033180 WO2020236611A1 (en) | 2019-05-17 | 2020-05-15 | Processes for forming 3-dimensional horizontal nor memory arrays |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2022532474A JP2022532474A (ja) | 2022-07-15 |
| JPWO2020236611A5 true JPWO2020236611A5 (ko) | 2023-05-01 |
Family
ID=73231329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021559384A Pending JP2022532474A (ja) | 2019-05-17 | 2020-05-15 | ３次元水平ｎｏｒ型メモリアレイの製造方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US11610909B2 (ko) |
| EP (1) | EP3970146A4 (ko) |
| JP (1) | JP2022532474A (ko) |
| KR (1) | KR20220008275A (ko) |
| CN (1) | CN113748466A (ko) |
| TW (1) | TWI743784B (ko) |
| WO (1) | WO2020236611A1 (ko) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11120884B2 (en) | 2015-09-30 | 2021-09-14 | Sunrise Memory Corporation | Implementing logic function and generating analog signals using NOR memory strings |
| US9842651B2 (en) | 2015-11-25 | 2017-12-12 | Sunrise Memory Corporation | Three-dimensional vertical NOR flash thin film transistor strings |
| TW202310429A (zh) | 2021-07-16 | 2023-03-01 | 美商日升存儲公司 | 薄膜鐵電電晶體的三維記憶體串陣列 |
| CN117916805A (zh) * | 2021-09-03 | 2024-04-19 | 日升存储公司 | 薄膜铁电晶体管的三维nor存储器串阵列 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1312120A1 (en) * | 2000-08-14 | 2003-05-21 | Matrix Semiconductor, Inc. | Dense arrays and charge storage devices, and methods for making same |
| US7365382B2 (en) * | 2005-02-28 | 2008-04-29 | Infineon Technologies Ag | Semiconductor memory having charge trapping memory cells and fabrication method thereof |
| KR20090106573A (ko) * | 2006-12-28 | 2009-10-09 | 샌디스크 코포레이션 | 비휘발성 메모리에서 필드 커플링 감소를 위한 차폐 플레이트들을 제조하는 방법 |
| US8547720B2 (en) * | 2010-06-08 | 2013-10-01 | Sandisk 3D Llc | Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines |
| US8946048B2 (en) * | 2010-06-19 | 2015-02-03 | Sandisk Technologies Inc. | Method of fabricating non-volatile memory with flat cell structures and air gap isolation |
| US8603890B2 (en) * | 2010-06-19 | 2013-12-10 | Sandisk Technologies Inc. | Air gap isolation in non-volatile memory |
| US8658499B2 (en) * | 2012-07-09 | 2014-02-25 | Sandisk Technologies Inc. | Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device |
| US9406693B1 (en) * | 2015-04-20 | 2016-08-02 | Sandisk Technologies Llc | Selective removal of charge-trapping layer for select gate transistors and dummy memory cells in 3D stacked memory |
| US9842651B2 (en) * | 2015-11-25 | 2017-12-12 | Sunrise Memory Corporation | Three-dimensional vertical NOR flash thin film transistor strings |
| US9892800B2 (en) * | 2015-09-30 | 2018-02-13 | Sunrise Memory Corporation | Multi-gate NOR flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates |
| US10121553B2 (en) | 2015-09-30 | 2018-11-06 | Sunrise Memory Corporation | Capacitive-coupled non-volatile thin-film transistor NOR strings in three-dimensional arrays |
| US10115732B2 (en) * | 2016-02-22 | 2018-10-30 | Sandisk Technologies Llc | Three dimensional memory device containing discrete silicon nitride charge storage regions |
| US9748332B1 (en) * | 2016-12-09 | 2017-08-29 | Macronix International Co., Ltd. | Non-volatile semiconductor memory |
| US10608011B2 (en) | 2017-06-20 | 2020-03-31 | Sunrise Memory Corporation | 3-dimensional NOR memory array architecture and methods for fabrication thereof |
| US10438964B2 (en) * | 2017-06-26 | 2019-10-08 | Sandisk Technologies Llc | Three-dimensional memory device having direct source contact and metal oxide blocking dielectric and method of making thereof |
| US10622377B2 (en) * | 2017-12-28 | 2020-04-14 | Sunrise Memory Corporation | 3-dimensional NOR memory array with very fine pitch: device and method |
-
2020
- 2020-05-14 TW TW109116042A patent/TWI743784B/zh active
- 2020-05-15 WO PCT/US2020/033180 patent/WO2020236611A1/en active Application Filing
- 2020-05-15 US US16/875,460 patent/US11610909B2/en active Active
- 2020-05-15 CN CN202080031720.8A patent/CN113748466A/zh active Pending
- 2020-05-15 KR KR1020217037443A patent/KR20220008275A/ko not_active Application Discontinuation
- 2020-05-15 JP JP2021559384A patent/JP2022532474A/ja active Pending
- 2020-05-15 EP EP20809132.2A patent/EP3970146A4/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7504302B2 (en) | Process of forming a non-volatile memory cell including a capacitor structure | |
| US6927145B1 (en) | Bitline hard mask spacer flow for memory cell scaling | |
| US7018868B1 (en) | Disposable hard mask for memory bitline scaling | |
| US20060281244A1 (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
| TWI227544B (en) | Nonvolatile memories and methods of fabrication | |
| US20140008714A1 (en) | Three Dimensional NAND Device and Method of Charge Trap Layer Separation and Floating Gate Formation in the NAND Device | |
| US20050196913A1 (en) | Floating gate memory structures and fabrication methods | |
| CN107305892B (zh) | 使用两个多晶硅沉积步骤来形成三栅极非易失性闪存单元对的方法 | |
| JP2007500953A (ja) | 不揮発性メモリデバイス | |
| JP2009212218A (ja) | 半導体記憶装置及びその製造方法 | |
| US7589374B2 (en) | Semiconductor device and related fabrication method | |
| US11610909B2 (en) | Processes for forming 3-dimensional horizontal NOR memory arrays | |
| TW202005061A (zh) | 具有鰭狀場效電晶體(finfet)結構之分離閘型非揮發性記憶體單元及邏輯裝置、及其製造方法 | |
| JP4226419B2 (ja) | プログラム及び消去特性が改善されたｓｏｎｏｓｅｅｐｒｏｍ及びその製造方法 | |
| CN111785723B (zh) | 一种分栅式存储器的制造方法 | |
| JP2006114922A (ja) | 第２の部分より深い第１の部分を有するトレンチの不揮発性メモリセル、そのメモリセルのアレイ及び製造方法 | |
| JP2000150676A (ja) | 不揮発性半導体記憶装置及びその製造方法 | |
| JP4606580B2 (ja) | 半導体不揮発性メモリの制御ゲートおよびフローティングゲートの形成 | |
| JP2000049244A (ja) | 半導体記憶装置及びその製造方法 | |
| JPWO2020236611A5 (ko) | ||
| US7560765B2 (en) | Nonvolatile memory device and method of fabricating the same | |
| JP4794837B2 (ja) | スプリットゲート型メモリ素子及びその製造方法 | |
| JP2000031305A (ja) | Ａｎｄ型不揮発性半導体記憶装置およびその製造方法 | |
| JP4558420B2 (ja) | スペーサー酸化工程を利用する分離ゲートフラッシュメモリセル製造方法 | |
| JP2008066725A (ja) | Ｅｅｐｒｏｍ装置及びその製造方法 |