JPWO2020170067A5 - - Google Patents

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Publication number
JPWO2020170067A5
JPWO2020170067A5 JP2021501127A JP2021501127A JPWO2020170067A5 JP WO2020170067 A5 JPWO2020170067 A5 JP WO2020170067A5 JP 2021501127 A JP2021501127 A JP 2021501127A JP 2021501127 A JP2021501127 A JP 2021501127A JP WO2020170067 A5 JPWO2020170067 A5 JP WO2020170067A5
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Japan
Prior art keywords
memory cell
directly connected
bit line
local bit
word line
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JP2021501127A
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English (en)
Japanese (ja)
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JPWO2020170067A1 (enExample
JP7480113B2 (ja
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Priority claimed from PCT/IB2020/051040 external-priority patent/WO2020170067A1/ja
Publication of JPWO2020170067A1 publication Critical patent/JPWO2020170067A1/ja
Publication of JPWO2020170067A5 publication Critical patent/JPWO2020170067A5/ja
Priority to JP2024070456A priority Critical patent/JP7702530B2/ja
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Publication of JP7480113B2 publication Critical patent/JP7480113B2/ja
Priority to JP2025105753A priority patent/JP2025138720A/ja
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JP2021501127A 2019-02-22 2020-02-11 半導体装置および当該半導体装置を有する電気機器 Active JP7480113B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2024070456A JP7702530B2 (ja) 2019-02-22 2024-04-24 半導体装置
JP2025105753A JP2025138720A (ja) 2019-02-22 2025-06-23 半導体装置

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019030030 2019-02-22
JP2019030030 2019-02-22
PCT/IB2020/051040 WO2020170067A1 (ja) 2019-02-22 2020-02-11 半導体装置および当該半導体装置を有する電気機器

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2024070456A Division JP7702530B2 (ja) 2019-02-22 2024-04-24 半導体装置

Publications (3)

Publication Number Publication Date
JPWO2020170067A1 JPWO2020170067A1 (enExample) 2020-08-27
JPWO2020170067A5 true JPWO2020170067A5 (enExample) 2023-01-31
JP7480113B2 JP7480113B2 (ja) 2024-05-09

Family

ID=72144825

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2021501127A Active JP7480113B2 (ja) 2019-02-22 2020-02-11 半導体装置および当該半導体装置を有する電気機器
JP2024070456A Active JP7702530B2 (ja) 2019-02-22 2024-04-24 半導体装置
JP2025105753A Pending JP2025138720A (ja) 2019-02-22 2025-06-23 半導体装置

Family Applications After (2)

Application Number Title Priority Date Filing Date
JP2024070456A Active JP7702530B2 (ja) 2019-02-22 2024-04-24 半導体装置
JP2025105753A Pending JP2025138720A (ja) 2019-02-22 2025-06-23 半導体装置

Country Status (5)

Country Link
US (2) US11968820B2 (enExample)
JP (3) JP7480113B2 (enExample)
KR (1) KR20210127721A (enExample)
CN (1) CN113454718B (enExample)
WO (1) WO2020170067A1 (enExample)

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Publication number Priority date Publication date Assignee Title
CN109213774B (zh) * 2018-08-01 2024-03-08 平安科技(深圳)有限公司 数据的存储方法及装置、存储介质、终端
WO2020170067A1 (ja) * 2019-02-22 2020-08-27 株式会社半導体エネルギー研究所 半導体装置および当該半導体装置を有する電気機器
US12457732B2 (en) 2019-08-22 2025-10-28 Semiconductor Energy Laboratory Co., Ltd. Memory cell and memory device
US12322652B2 (en) * 2022-05-09 2025-06-03 International Business Machines Corporation Local interconnect for cross coupling
US20230369218A1 (en) * 2022-05-11 2023-11-16 International Business Machines Corporation Interlevel via for stacked field-effect transistor device
JP2023177534A (ja) * 2022-06-02 2023-12-14 キオクシア株式会社 メモリデバイス
WO2024028682A1 (ja) * 2022-08-02 2024-02-08 株式会社半導体エネルギー研究所 半導体装置及び電子機器
TWI857842B (zh) * 2023-11-08 2024-10-01 旺宏電子股份有限公司 三維記憶體
US12406735B2 (en) 2023-11-08 2025-09-02 Macronix International Co., Ltd. 3D memory

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Publication number Priority date Publication date Assignee Title
JP2001185700A (ja) * 1999-12-27 2001-07-06 Mitsubishi Electric Corp 半導体記憶装置
KR100935936B1 (ko) 2007-09-12 2010-01-11 삼성전자주식회사 적층 메모리 장치
US7898893B2 (en) * 2007-09-12 2011-03-01 Samsung Electronics Co., Ltd. Multi-layered memory devices
KR20100120080A (ko) 2009-05-04 2010-11-12 삼성전자주식회사 적층 메모리 소자
JP2010263211A (ja) 2009-05-04 2010-11-18 Samsung Electronics Co Ltd 積層メモリ素子
JP2011204829A (ja) 2010-03-25 2011-10-13 Toshiba Corp 半導体記憶装置
JP2012256821A (ja) 2010-09-13 2012-12-27 Semiconductor Energy Lab Co Ltd 記憶装置
US20120307545A1 (en) * 2011-06-01 2012-12-06 Texas Instruments Incorporated Interleaved Bit Line Architecture for 2T2C Ferroelectric Memories
JP2013065638A (ja) 2011-09-15 2013-04-11 Elpida Memory Inc 半導体装置
JP6635670B2 (ja) 2014-04-11 2020-01-29 株式会社半導体エネルギー研究所 半導体装置
WO2015170220A1 (en) 2014-05-09 2015-11-12 Semiconductor Energy Laboratory Co., Ltd. Memory device and electronic device
CN106796918A (zh) * 2014-10-10 2017-05-31 株式会社半导体能源研究所 半导体装置、电路板及电子设备
US9786383B2 (en) * 2015-02-25 2017-10-10 Ememory Technology Inc. One time programmable non-volatile memory and read sensing method thereof
WO2016181256A1 (ja) * 2015-05-12 2016-11-17 株式会社半導体エネルギー研究所 半導体装置、電子部品および電子機器
US10319743B2 (en) 2016-12-16 2019-06-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display system, and electronic device
JP2018133016A (ja) 2017-02-17 2018-08-23 株式会社半導体エネルギー研究所 ニューラルネットワークシステム
JP2018201003A (ja) * 2017-05-26 2018-12-20 株式会社半導体エネルギー研究所 半導体装置及び電子機器
WO2018220491A1 (ja) 2017-06-02 2018-12-06 株式会社半導体エネルギー研究所 半導体装置、電子部品及び電子機器
JP6975560B2 (ja) * 2017-06-23 2021-12-01 株式会社半導体エネルギー研究所 記憶装置
US10395710B1 (en) * 2018-05-21 2019-08-27 Avalanche Technology, Inc. Magnetic memory emulating dynamic random access memory (DRAM)
WO2020170067A1 (ja) * 2019-02-22 2020-08-27 株式会社半導体エネルギー研究所 半導体装置および当該半導体装置を有する電気機器
JP7535032B2 (ja) * 2019-02-22 2024-08-15 株式会社半導体エネルギー研究所 エラー検出機能を有する記憶装置、半導体装置、および、電子機器

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