JPWO2020044943A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JPWO2020044943A1 JPWO2020044943A1 JP2020540185A JP2020540185A JPWO2020044943A1 JP WO2020044943 A1 JPWO2020044943 A1 JP WO2020044943A1 JP 2020540185 A JP2020540185 A JP 2020540185A JP 2020540185 A JP2020540185 A JP 2020540185A JP WO2020044943 A1 JPWO2020044943 A1 JP WO2020044943A1
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- H01L2224/8034—Bonding interfaces of the bonding area
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- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
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- H01L2224/808—Bonding techniques
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Abstract
Description
1.半導体装置
2.配線利用の導電体
3.接合面
4.製造工程
5.電源配線への適用例
6.内視鏡手術システムへの応用例
7.移動体への応用例
[固体撮像装置の構成]
図1は、本技術の実施の形態における半導体装置の一例である固体撮像装置の構成例を示す図である。この固体撮像装置は、CMOS(Complementary Metal Oxide Semiconductor)イメージセンサとして構成される。この固体撮像装置は、(図示しない)半導体基板(例えば、シリコン基板)に、撮像素子10および周辺回路部を有する。周辺回路部は、垂直駆動回路20と、水平駆動回路30と、制御回路40と、カラム信号処理回路50と、出力回路60とを備える。
図3は、本技術の実施の形態における固体撮像装置の基板の分割と接合面との関係例を示す図である。
[配線利用の形態]
図5は、本技術の実施の形態において配線として利用される銅配線202および302の構造例を示す第1の図である。
図11は、本技術の実施の形態において配線として利用される銅配線202および302の接合例を示す第1の図である。
[フロアプラン]
図14は、本技術の実施の形態における接合面99のフロアプランの第1の例を示す図である。
[固体撮像装置の構造]
図21は、本技術の実施の形態における固体撮像装置100の一例を示す断面図である。この固体撮像装置100は、裏面照射型のCMOS固体撮像素子であり、受光部が回路部の上部に配置される。
図24は、本技術の実施の形態における接続配線369と配線371との間の接続孔363の第1の配置例を示す図である。ここでは、接合面における配線を太幅の電源線にリベット打ちした構造を想定する。
図26乃至図33は、本技術の実施の形態における固体撮像装置の製造方法の一例を示す図である。なお、画素アレイを有する第1の半導体基板200側の工程、ロジック回路を有する第2の半導体基板300側の工程は省略して示す。
上述の実施の形態では第1の半導体基板81および第2の半導体基板82を積層していたが、さらに他の半導体基板を積層してもよい。
[アナログ電源の強化]
図35は、本技術の実施の形態における半導体基板600におけるフロアプランの例を示す図である。この例は、アナログ回路の電源配線として接合面付近の導電体、ここでは銅、の配線利用を適用したものである。
[デジタル電源の強化]
図41は、本技術の実施の形態における入出力パッド690からの配線引出しの例を示す図である。
図42は、本技術の実施の形態における電源配線リング680への配線利用683の適用例を示す図である。
本開示に係る技術(本技術)は、様々な製品へ応用することができる。例えば、本開示に係る技術は、内視鏡手術システムに適用されてもよい。
本開示に係る技術(本技術)は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。
(1)それぞれに多層配線層が形成される複数の半導体基板の前記多層配線層間が電気的に接続されて接合された積層半導体基板において、
前記複数の半導体基板の接合面付近に形成される導電体を接合面方向に通電させる半導体装置。
(2)前記接合面付近に形成される導電体の少なくとも一部は、接続孔接続面の幅に対して2倍以上の平面長辺を有する
前記(1)に記載の半導体装置。
(3)前記接合面付近に形成される導電体の少なくとも一部は、前記接合面において相対する前記導電体のうち一方のみが前記半導体基板に接続孔を有する
前記(1)または(2)に記載の半導体装置。
(4)前記接合面付近に形成される導電体の少なくとも一部は、他方の前記半導体基板における前記導電体と電気的に接続しない
前記(1)から(3)のいずれかに記載の半導体装置。
(5)前記接合面付近に形成される導電体の少なくとも一部は、前記接合面において相対する前記導電体の形状が互いに異なる
前記(1)から(4)のいずれかに記載の半導体装置。
(6)前記接合面付近に形成される導電体の少なくとも一部は、前記接合面において相対する前記導電体が前記接合面方向に互いに所定の距離ずれて接合される
前記(1)から(5)のいずれかに記載の半導体装置。
(7)前記接合面付近に形成される導電体の少なくとも一部は、平面アスペクト比が1より大きい形状である
前記(1)から(6)のいずれかに記載の半導体装置。
(8)前記接合面付近に形成される導電体の少なくとも一部は、前記接合面において相対する前記導電体が前記接合面において長手方向に互いに直交して接合される
前記(7)に記載の半導体装置。
(9)前記接合面付近に形成される導電体の少なくとも一部は、前記接合面において相対する前記導電体が前記接合面において長手方向に互いに並行して接合される
前記(7)に記載の半導体装置。
(10)前記接合面付近に形成される導電体の少なくとも一部は、平面アスペクト比が1より大きい矩形形状または楕円形状である
前記(1)から(9)のいずれかに記載の半導体装置。
(11)前記接合面付近に形成される導電体の少なくとも一部は、平面アスペクト比が1より大きい矩形の合成からなる多角形状である
前記(1)から(9)のいずれかに記載の半導体装置。
(12)前記接合面付近に形成される導電体の少なくとも一部は、入出力パッドの内側の周囲を囲む領域に設けられる
前記(1)から(11)のいずれかに記載の半導体装置。
(13)前記接合面付近に形成される導電体の少なくとも一部は、入出力パッドの内側の矩形状の領域に設けられる
前記(1)から(11)のいずれかに記載の半導体装置。
(14)前記接合面付近に形成される導電体の少なくとも一部は、電源配線と並行して設けられる
前記(1)から(11)のいずれかに記載の半導体装置。
11 画素
12 電流パス
19 垂直信号線(VSL)
20 垂直駆動回路
30 水平駆動回路
40 制御回路
50 カラム信号処理回路
59 水平信号線
60 出力回路
81、82 半導体基板
83 画素領域
84 制御回路
85 ロジック回路
86 アナログ回路
91 ダミーの銅配線
92 接続孔を有する銅配線
93 配線利用の銅配線
94 シールド利用の銅配線
98 入出力(IO)パッド
99 接合面
100 固体撮像装置
200、300、400、600 半導体基板
201〜203、301〜303 銅配線
209、309 接続孔
610 ロジック回路
620 アナログマクロ
631 電源配線(最上層の下層)
632 電源配線(最上層)
633 配線利用
661 被保護素子
662 保護回路
663 抵抗
680 電源配線リング
682 配線
683 配線利用
690 入出力(IO)パッド
Claims (14)
- それぞれに多層配線層が形成される複数の半導体基板の前記多層配線層間が電気的に接続されて接合された積層半導体基板において、
前記複数の半導体基板の接合面付近に形成される導電体を接合面方向に通電させる半導体装置。 - 前記接合面付近に形成される導電体の少なくとも一部は、接続孔接続面の幅に対して2倍以上の平面長辺を有する
請求項1記載の半導体装置。 - 前記接合面付近に形成される導電体の少なくとも一部は、前記接合面において相対する前記導電体のうち一方のみが前記半導体基板に接続孔を有する
請求項1記載の半導体装置。 - 前記接合面付近に形成される導電体の少なくとも一部は、他方の前記半導体基板における前記導電体と電気的に接続しない
請求項1記載の半導体装置。 - 前記接合面付近に形成される導電体の少なくとも一部は、前記接合面において相対する前記導電体の形状が互いに異なる
請求項1記載の半導体装置。 - 前記接合面付近に形成される導電体の少なくとも一部は、前記接合面において相対する前記導電体が前記接合面方向に互いに所定の距離ずれて接合される
請求項1記載の半導体装置。 - 前記接合面付近に形成される導電体の少なくとも一部は、平面アスペクト比が1より大きい形状である
請求項1記載の半導体装置。 - 前記接合面付近に形成される導電体の少なくとも一部は、前記接合面において相対する前記導電体が前記接合面において長手方向に互いに直交して接合される
請求項7記載の半導体装置。 - 前記接合面付近に形成される導電体の少なくとも一部は、前記接合面において相対する前記導電体が前記接合面において長手方向に互いに並行して接合される
請求項7記載の半導体装置。 - 前記接合面付近に形成される導電体の少なくとも一部は、平面アスペクト比が1より大きい矩形形状または楕円形状である
請求項1記載の半導体装置。 - 前記接合面付近に形成される導電体の少なくとも一部は、平面アスペクト比が1より大きい矩形の合成からなる多角形状である
請求項1記載の半導体装置。 - 前記接合面付近に形成される導電体の少なくとも一部は、入出力パッドの内側の周囲を囲む領域に設けられる
請求項1記載の半導体装置。 - 前記接合面付近に形成される導電体の少なくとも一部は、入出力パッドの内側の矩形状の領域に設けられる
請求項1記載の半導体装置。 - 前記接合面付近に形成される導電体の少なくとも一部は、電源配線と並行して設けられる
請求項1記載の半導体装置。
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US20210351219A1 (en) | 2021-11-11 |
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