JPWO2018211992A1 - 電子部品搭載用基板及びその製造方法 - Google Patents
電子部品搭載用基板及びその製造方法 Download PDFInfo
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- JPWO2018211992A1 JPWO2018211992A1 JP2019519176A JP2019519176A JPWO2018211992A1 JP WO2018211992 A1 JPWO2018211992 A1 JP WO2018211992A1 JP 2019519176 A JP2019519176 A JP 2019519176A JP 2019519176 A JP2019519176 A JP 2019519176A JP WO2018211992 A1 JPWO2018211992 A1 JP WO2018211992A1
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
- H05K3/385—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by conversion of the surface of the metal, e.g. by oxidation, whether or not followed by reaction or removal of the converted layer
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H05K13/04—Mounting of components, e.g. of leadless components
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- H05K2201/03—Conductive materials
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Abstract
Description
本実施形態では、絶縁体層が絶縁層である場合について説明する。本実施形態に係る電子部品搭載用基板の製造方法は、以下に述べる密着層形成工程及び導体形成工程を順に備える。本開示の絶縁層上に一部又は全部の絶縁性物質による密着層及び導体を形成する密着層形成工程及び導体形成工程の一例を、図1(a)から図1(e)に示す。図1(a)から図1(e)において、11は絶縁層、12は導体、13はパターンレジスト、21は一部又は全部の絶縁性物質による密着層を示す。
後述する一部又は全部の絶縁性物質による第二の密着層も同様である。
本実施形態では、第1の実施形態で説明した電子部品搭載用基板が、絶縁層及び導体の組合せの層が絶縁層上に形成されている多層基板である例について説明する。本実施形態に係る電子部品搭載用基板は、前記組合せの層に密着層が設けられている。
図21に、本開示の実施形態に係る電子部品搭載用基板の一例を示す。導体12は、密着層21側の最下層に、無電解めっき層121を含む。例えば、導体12は、密着層21側の最下層から、順に、無電解めっき層121及び電解めっき層122が積層されている。このように、密着層21と無電解めっき層121が接していることで、密着層21及び導体12の密着強度を高めることができる。
本実施の形態の電子部品搭載用基板等の基板は、図27に示すように、絶縁層11と、絶縁層11に設けられた密着層200と、密着層200に設けられた金属層220と、を有してもよい。密着層200は、密着本体層210と、密着本体層210のおもて面から突出したアンカー体215とを有してもよい。金属層220にパターニングが施されて、図29に示すように導体12となってもよい。導体12は金属層220の一形態であり、金属層220に含まれる概念である。
本実施の形態の電子部品搭載用基板等の基板は、図31に示すように、絶縁層11と、絶縁層11に設けられた密着層200と、密着層200に設けられた金属層220と、を有してもよい。密着層200は酸化還元層250を有してもよい。酸化還元層250は、金属層220を酸化させる酸化層又は還元させる還元層である。このような酸化還元層250を設けることで、金属層220と酸化還元層250とが酸化還元反応等の化学反応を起こして、これらの層を互いに密着させることができる。
2CuO+C→2Cu+CO2
図33に示すように、導体12が密着層200を貫通するように押し込まれてもよい。この場合には、導体12の側面に密着層200が設けられ、底面には密着層200が設けられないことになる。
本実施形態では、本開示に係る電子部品搭載用基板の適用例について説明する。本実施形態に係る電子部品は、本開示に係る電子部品搭載用基板を備え、本開示に係る電子部品搭載用基板を用いて予め定められた処理を実行する。処理は電子部品による任意の処理である。
111−1、111−2、111−3、111−4、111−5、111−6、111−7:凹部
112−1、112−6、112−9:凸部
113:トンネル
12、12−1、12−2、12−3:導体
121:無電解めっき層
122:電解めっき層
13:パターンレジスト
14、14−1、14−2、14−3:絶縁層
15:VIA
21:一部又は全部の絶縁性物質による密着層
22:一部又は全部の絶縁性物質による第二の密着層
Claims (15)
- 絶縁層と、
前記絶縁層に設けられた密着層と、
前記密着層に設けられた金属層と、
を備え、
前記密着層は、密着本体層と、前記密着本体層のおもて面から突出したアンカー体とを有する、又は、酸化還元層を有することを特徴とする基板。 - 前記密着層は前記酸化還元層を有し、
前記酸化還元層のうち、前記金属層との境界では、前記金属層を構成する金属と当該金属の金属酸化物とが混在していることを特徴とする請求項1に記載の基板。 - 前記密着層は前記酸化還元層を有し、
前記酸化還元層のうち、前記金属層との境界では、前記酸化還元層を構成する第一材料と当該第一材料の還元物とが混在していることを特徴とする請求項1又は2のいずれかに記載の基板。 - 前記密着層は前記酸化還元層を有し、
前記酸化還元層は、酸化還元本体層と、前記酸化還元本体層の前記金属層側に設けられた境界層とを有し、
前記境界層では、前記金属層を構成する金属と当該金属の金属酸化物とが混在している、又は、前記酸化還元層を構成する第一材料と当該第一材料の還元物とが混在していることを特徴とする請求項1乃至3のいずれか1項に記載の基板。 - 前記酸化還元本体層は、前記絶縁層に直接設けられることを特徴とする請求項4に記載の基板。
- 前記密着層は、密着本体層と、前記密着本体層のおもて面から突出したアンカー体とを有し、
前記アンカー体は粒状物質であり、
前記粒状物質の一部が前記密着本体層内に埋設していることを特徴とする請求項1に記載の基板。 - 前記粒状物質は窒化物であることを特徴とする請求項6に記載の基板。
- 前記密着本体層はレジスト層又はインク層であることを特徴とする請求項6又は7のいずれかに記載の基板。
- 一つ以上の粒状物質は前記密着本体層で横断面における最大の面積を有することを特徴とする請求項6乃至8のいずれか1項に記載の基板。
- 前記金属層はパターニングされた導体からなり、
前記導体は、底面及び側面の少なくとも一部が、前記密着層のおもて面よりも裏面側に位置していることを特徴とする請求項1乃至9のいずれか1項に記載の基板。 - 前記導体の側面及び底面に前記密着層が設けられることを特徴とする請求項10に記載の基板。
- 前記導体の側面に前記密着層が設けられ、前記導体の底面に密着層が設けられないことを特徴とする請求項10に記載の基板。
- 前記絶縁層は、積層された複数の積層絶縁層を有し、
前記密着層は、積層された複数の積層密着層を有し、
前記積層絶縁層に前記積層密着層が設けられ、
前記積層密着層に前記金属層が設けられることを特徴とする請求項1乃至12のいずれか1項に記載の基板。 - 請求項1乃至13のいずれか1項に記載の基板と、
前記基板に設けられた電子部品と、
を備え、
前記電子部品は前記導体に設けられていることを特徴とする電子装置。 - 請求項14に記載の電子装置を備えた実装装置。
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PCT/JP2018/017503 WO2018211992A1 (ja) | 2017-05-19 | 2018-05-02 | 電子部品搭載用基板及びその製造方法 |
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WO2018211992A1 (ja) | 2018-11-22 |
JP6775083B2 (ja) | 2020-10-28 |
CN110771270B (zh) | 2023-05-30 |
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